Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024
Document Table of Contents

2.4.1. System Clock

Specifying the clock constraints in every Nios® V processor system is an important system design consideration and is required for correctness and deterministic behavior. The Quartus® Prime Timing Analyzer performs static timing analysis to validate the timing performance of all logic in your design using industry-standard constraint, analysis, and reporting methodology.

Basic 100 MHz Clock with 50/50 Duty Cycle

# Create 100MHz Clock
create_clock -name {clk} -period 10 [get_ports {clk}]