Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024

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Document Table of Contents Hardware Design Flow

The following sections describe the steps for building a bootable system for a Nios® V processor application, which executes in place from the configuration QSPI flash.

The following example is built using an Intel Arria 10 SoC Development Kit.

IP Component Settings

  1. Create your Nios® V processor project using Quartus® Prime and Platform Designer.
  2. Add Generic Serial Flash Interface Intel FPGA IP into your Platform Designer.
    Figure 18. Connections for Nios® V Processor Project
    Figure 19. Generic Serial Flash Interface Intel FPGA IP Parameter Settings
  3. Change the Device Density (Mb) according to the QSPI flash size.
  4. Change the addressing mode by modifying bit 8 of the Control Register value in the Default Settings parameter section. Changing bit 8 to 0x0 enables 3-byte addressing, or 0x1 enables 4-byte addressing.
Note: Refer to Intel Supported Configuration Devices tab > Intel Supported Third Party Configuration Devices in the Device Configuration Support Center to check the byte addressing mode supported for each flash device in each Intel FPGA device.

For example, Arria® 10 devices support the 4-byte addressing mode when used with Micron flash devices .

Reset Agent Settings for Nios® V Processor Execute-In-Place Method

  1. In the Nios® V processor IP parameter editor, set the Reset Agent to QSPI Flash.
    1. Your (.sof) image size influences your reset offset configuration. The reset offset is the start address of the HEX file in QSPI flash and it must point to a location after the (.sof) image. If the (.sof) image space and the reset offset location overlap, Quartus® Prime software displays an overlap error. You can determine the minimum reset offset by using the configuration bitstream size from the device datasheet.
      Refer to the following example:
      • The uncompressed configuration bitstream size for Arria® 10 GX 660 is 252,959,072 bits (31,619,884 bytes).
      • If the SOF image starts at address 0x0, the SOF image can extend up to address 0x1E27B2C. In this case, the minimum reset offset you can select to avoid overlap errors is 0x1E27B30.
      • Altera recommends you to use a flash sector boundary address for the reset offset. Doing so allows you to update the application software image at a later time without interfering with the FPGA image.
      Figure 20. Parameter Editor Settings
  2. Click Generate HDL, the Generation dialog box appears.
  3. Specify output file generation options and then click Generate.

Quartus® Prime Software Settings

  1. In the Quartus® Prime software, click Assignment > Device > Device and Pin Options > Configuration.
  2. Set Configuration scheme to Active Serial x4 (can use Configuration Device).
  3. Set the Active serial clock source to 100 MHz Internal Oscillator.
    Figure 21. Device and Pin Options
  4. Click OK to exit the Device and Pin Options window.
  5. Click OK to exit the Device window.
  6. Click Start Compilation to compile your project.