Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

8.2.7. Operating the Example Design

To display the application messages, the example design utilizes the JTAG UART Intel FPGA IP. You can begin the display message by using the following command:

Figure 132. Output Result from PE1
Figure 133. Output Result from PE2