Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024
Document Table of Contents

8.3.2. Overview

You can download the CRC Custom Instruction Design on Nios® V/g processor in the Intel® FPGA Design Store. The example designs are based on the Agilex™ 7 F-Series FPGA Development Kit. Use the scripts to generate and programme the hardware and software design as SRAM Object Files (.sof) and Executable and Linking Format (.elf) into the device.

The example design connects a custom logic CRC processing engine to a Nios® V processor system. In the Nios® V software application, the processor feeds the same checksum data into three CRC decoders (custom logic CRC processing engine, CRC software algorithm, and optimized CRC software algorithm). All three CRC decoders return the same CRC results, and the latency is compared among themselves.