Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024

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2.4.3. Reset Release IP

Intel SDM-based devices use a parallel, sector-based architecture that distributes the core fabric logic across multiple sectors. Altera recommends you to use the Reset Release Intel® FPGA IP as one of the initial inputs to the reset circuit. Intel® SDM-based devices includes Stratix® 10, and Agilex™ devices. Control-block based devices are not affected by this requirement.