Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024
Document Table of Contents Hardware Design Flow

The following sections describe a step-by-step method for building a bootable system for a Nios® V processor application from OCRAM. The example below is built using Intel Arria 10 SoC development kit.

IP Component Settings

  1. Create your Nios® V processor project using Quartus® Prime and Platform Designer.
  2. Ensure the On-Chip Memory (RAM or ROM) Intel FPGA is added into your Platform Designer system.
  3. Enable Initialize memory content and Enable non-default initialization file with ram.hex in the on-chip memory.
Figure 72. Connections for Nios® V Processor Project
Figure 73. On-Chip Memory (RAM or ROM) Intel FPGA IP Parameter Settings

Reset Agent Settings for Nios® V Processor

  1. In the Nios® V processor parameter editor, set the Reset Agent to OCRAM
    Figure 74.  Nios® V Processor Parameter Editor Settings
  2. Click Generate HDL, the Generation dialog box appears.
  3. Specify output file generation options and then click Generate.

Quartus® Prime Settings

  1. In the Intel Quartus Prime software, click Assignment > Device > Device and Pin Options > Configuration.
  2. Set Configuration scheme according to your FPGA configuration scheme
  3. Click OK to exit the Device and Pin Options window.
  4. Click OK to exit the Device window.
  5. Click Start Compilation to compile your project.