Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024
Document Table of Contents CPU Architecture

Table 8.  CPU Architecture Tab Parameters
CPU Architecture Description
Enable Pipelining in CPU
  • Enable this option to instantiate pipelined Nios® V/m processor.
    • IPC is higher at the cost of higher logic area and lower Fmax frequency.
  • Disable this option to instantiate non-pipelined Nios® V/m processor.
    • Has similar core performance with the Nios® V/c processor.
    • Supports debugging and interrupt capability
    • Lower logic area and higher Fmax frequency at the cost of lower IPC.
mhartid CSR value
  • Hart ID register (mhartid) value is 0 at default.
  • Assign a value between 0 and 4094.
  • Compatible with Intel FPGA Avalon® Mutex Core HAL API.