Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024
Document Table of Contents

2.4.2. Reset Request Interface

Nios® V processor includes an optional reset request facility. The reset request facility consists of reset_req and reset_req_ack signals.

To enable the reset request in Platform Designer:
  1. Launch the Nios® V Processor IP Parameter Editor.
  2. On the Use Reset Request setting, turn on the Add Reset Request Interface option.
    Figure 10. Enable Nios® V Processor Reset Request

The reset_req signal acts like an interrupt. When you assert the reset_req, you are requesting reset to the core. The core waits for any outstanding bus transaction to complete its operation. For example, if there is a pending memory access transaction, core waits for a complete response. Similarly, core accepts any pending instruction response but does not issue instruction request after receiving the reset_req signal.

The reset operation consists of the following flow:
  1. Complete all pending operation
  2. Flush internal pipeline
  3. Set the instruction Program Counter to reset vector
  4. Reset core

The whole reset operation takes a few clock cycles. The reset_req must remain asserted until reset_req_ack is asserted indicating core reset operation has successfully completed. Failure to do so results in core’s state being non-deterministic.