Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024
Public
Document Table of Contents

6.1. Debugging Nios® V/c Processor

Nios® V/c processor implements the compact architecture to achieve a smaller logic size by applying the following trait:
  • Non-pipelined datapath
  • No debug module
  • No processor CSR
  • No interrupts and exceptions
  • No internal timer module

The Nios® V/c processor core is limited to hardware debugging without the debug module. Software debugging is not applicable for the Nios® V/c processor core.