Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024
Document Table of Contents

2.3.4. Caches

On-chip memories are commonly used to implement the cache functionality because of their low latency. The Nios® V processor uses on-chip memory for its instruction and data caches. The limited capacity of on-chip memory is usually not an issue for caches because they are typically small.

Caches are commonly used under the following conditions:

  • Regular memory is located off-chip and has a longer access time than on-chip memory.
  • The performance-critical sections of the software code can fit in the instruction cache, improving system performance.
  • The performance-critical, most frequently used section of the data can fit in the data cache, improving system performance.