Nios® V Embedded Processor Design Handbook

ID 726952
Date 5/13/2024
Document Table of Contents

6.6. Simulating Nios® V Processor Designs

This section describes the following tasks:
  • Generating an RTL simulation environment with Nios® V processor example designs and Platform Designer.
  • Running the RTL simulation in the Questa* Intel® FPGA Edition simulator.

The increasing pressure to deliver robust products to market timely has amplified the importance of comprehensively verifying embedded processor designs. Therefore, consider the verification solution supplied with the processor when choosing an embedded processor. Nios® V embedded processor designs support a broad range of verification solutions, including the following:

  • Board Level Verification—Intel offers several development boards that provide a versatile platform for verifying both the hardware and software of a Nios V embedded processor system. You can further debug the hardware components that interact with the processor with the Signal Tap embedded logic analyzer.
  • Register Transfer Level (RTL) Simulation—RTL simulation is a powerful means of debugging the interaction between a processor and its peripheral set. When debugging a target board, it is often difficult to view signals buried deep in the system. RTL simulation alleviates this problem by enabling you to probe every register and signal in the design. You can easily simulate Nios® V based systems in the Questa* Intel® FPGA Edition simulator with an automatically generated simulation environment, that is Platform Designer.
Note: Due to a limitation with embedded memory blocks, the simulation model of Nios® V processor does not support ECC on Arria® 10 devices.