Intel® Arria® 10 Hard Processor System Technical Reference Manual

ID 683711
Date 1/10/2023
Public

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8.3.4.6.1. Example: One Master Always Takes Precedence

In this example, one particular master's packets always take precedence.

Consider a system that includes three masters, A, B, and C. In this system, we require that master A always takes precedence over master B at each arbitration node, and master B always takes precedence over master C. To implement this arbitration scheme, we configure all QoS generators in fixed mode, and assign appropriate values for read and write urgency, as shown in the following table:

Table 65.  Fixed Example Settings
Master QoS Mode P1 (Read Urgency) P0 (Write Urgency)
A Fixed (mode 0) 0x3 0x3
B Fixed (mode 0) 0x2 0x2
C Fixed (mode 0) 0x1 0x1

In fixed mode, masters by default have a read urgency of 1 and write urgency of 0. So master C has equal urgency for reads and higher urgency for writes compared to all the other masters in the system.