Intel Agilex® 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

ID 683301
Date 12/04/2023
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Document Revision History for the Intel Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series

Document Version Changes
2023.12.04
  • Added AGF 006 and AGF 012 R24D package in the Data Sheet Status for Intel Agilex 7 FPGAs and SoCs F-Series table.
  • Added footnote in F-Tile FGT Electrical Compliance List table.
  • Removed XSR support in CEI 4.0/5.0 in the F-Tile FHT Electrical Compliance List table.
2023.10.02
  • Added AGF 008 and AGF 014 R24D package in the Data Sheet Status for Intel Agilex 7 FPGAs and SoCs F-Series table.
  • Updated the status from Advance to Preliminary for AGI 041 R29D package in the Data Sheet Status for Intel Agilex 7 FPGAs and SoCs I-Series table.
  • Updated supported –2 transceiver speed grade data rate for NRZ in the F-Tile FGT Transmitter and Receiver Data Rate Performance table.
  • Updated the CONF_DONE and INIT_DONE signals in the General Configuration Timing Diagram and added a note for the signals.
2023.06.26
  • Updated supported data rate for NRZ in the F-Tile FGT Transmitter and Receiver Data Rate Performance table.
  • Added table description in the F-Tile FHT Reference Clocks Input Specifications table.
  • Updated the F-Tile FGT Reference Clock Input Specifications table.
    • Added supported I/O standards.
    • Added footnote to ZREF-DIFF-DC.
  • Added diagram: Simplified F-Tile FGT Reference Clock Input Buffer.
  • Updated VTX-CM OUT, ZRL-DIFF-DC, ZRL-DIFF-NYQ, and ZRL-CMN specifications in the F-Tile FHT Transmitter Electrical Specification table.
  • Updated ZRL-DIFF-DC, ZRL-DIFF-NYQ, and ZRL-CMN specifications in the F-Tile FGT Transmitter Electrical Specifications table.
  • Updated VRX-CM-DC, ZRL-DIFF-DC, ZRL-DIFF-NYQ, ZRL-CM specifications in the F-Tile FHT Receiver Electrical Specifications table.
  • Updated the F-Tile FGT Receiver Electrical Specifications table.
    • Added footnote to VRX-DIFF-PKPK
    • Updated footnote to VRX-CM-DC, IINS-LOSS-30Gb/s, and IINS-LOSS-25Gb/s.
    • Updated VRX-DIFF-PKPK, IINS-LOSS-56Gb/s, IINS-LOSS-30Gb/s, IINS-LOSS-25Gb/s, ZRL-DIFF-DC, ZRL-DIFF-NYQ, and ZRL-CM specifications..
  • Updated the F-Tile FGT Electrical Compliance List table.
    • Updated lane rate for JESD204C protocol.
    • Updated specification/clause for SerialLite IV protocol.
2023.04.19 Added AGI 041 R31B package in the Data Sheet Status for Intel Agilex Devices (I-Series) table.
2023.04.03
  • Updated the Absolute Maximum Ratings table.
    • Updated VCCH (for R-Tile and F-Tile devices), VCCH_SDM (for R-Tile and F-Tile devices), VCCEHT_GXR, VCCERT_GXR, VCCED_GXR, VCCE_PLL_GXR, VCCE_DTS_GXR, VCCCLK_GXR, VCCHFUSE_GXR, VCC_HSSI_GXR, and VCCH_FGT_GXF specifications.
    • Added VCC_HSSI_GXF, VCCFUSECORE_GXF, VCCFUSEWR_GXF, and VCCCLK_GXF specifications.
  • Updated VCCH (for R-Tile and F-Tile devices) and VCCH_SDM (for R-Tile and F-Tile devices) in the Recommended Operating Conditions table.
  • Updated the simple quad-port RAM specification for –2V speed grade in the Memory Block Performance Specifications table.
  • Updated specifications for AGF 006/008 and AGI 019/023 in the Configuration Bit Stream Sizes table.
2023.02.20
  • Updated product family name to "Intel Agilex 7".
  • Retitled the document from Intel Agilex F-Series and I-Series Device Data Sheet to Intel Agilex 7 FPGAs and SoCs Device Data Sheet: F-Series and I-Series.
  • Added AGI 041 R29D package in the following tables:
    • Data Sheet Status for Intel Agilex 7 FPGAs and SoCs I-Series
    • Configuration Bit Stream Sizes
  • Updated the status from Advance to Preliminary for the following devices in the Data Sheet Status for Intel Agilex 7 FPGAs and SoCs I-Series table:
    • AGI 019/023 R18A package
    • AGI 022/027 R29A package
    • AGI 019/022/023/027 R31B package
    • AGI 035/040 R39A package
  • Updated VCCH_GXR[L,R] and VCCRT_GXR[L,R] specifications in the R-Tile Transceiver Power Supply Recommended Operating Conditions table.
  • Added quad SPI flash size to store periphery image in the Configuration Bit Stream Sizes table.
2022.12.19
  • Added AGI 022/027 R31A package in the Data Sheet Status for Intel Agilex Devices (I-Series) table.
  • Updated table description for the AS Timing Parameters table.
  • Added Tdcsb2b symbol in the AS Configuration Serial Output Timing Diagram.
  • Updated specifications for AGI 022 and AGI 027 devices in the Configuration Bit Stream Sizes table.
2022.11.01
  • Renamed document title from Intel Agilex Device Data Sheet to Intel Agilex F-Series and I-Series Device Data Sheet.
  • Removed device name in tables and descriptions.
  • Changed the status for AGF 019/023 R25A package from Preliminary to Final in the Data Sheet Status for Intel Agilex Devices (F-Series) table.
  • Removed conditions for CXL 2.5 GT/s and CXL 5 GT/s in the R-Tile Slow PLL Performance table.
  • Updated typical frequency specification in the F-Tile FHT Reference Clock Requirements table.
  • Updated VREFIN-CM-AC in the F-Tile FHT Reference Clocks Input Specifications table.
  • Updated the parameter and description, and added a footnote for VREFIN-DIFF in the F-Tile FGT Reference Clock Input Specifications table.
  • Added VTX-CM OUT specifications in the following tables:
    • F-Tile FHT Transmitter Electrical Specifications
    • F-Tile FGT Transmitter Electrical Specifications
2022.07.04
  • Added AGI 035/040 R39A package in the Data Sheet Status for Intel Agilex Devices (I-Series) table.
  • Added VCCH_SDM specifications for F-tile devices in the Recommended Operating Conditions for Intel Agilex Devices table.
  • Updated ZTX-DIFF-DC description and specifications in the F-Tile FGT Transmitter Electrical Specifications table.
  • Updated RDIFF-DC specifications in the F-Tile FGT Receiver Electrical Specifications table.
  • Added specifications for AGI 035 and AGI 040 devices in the Configuration Bit Stream Sizes for Intel Agilex Devices table.
2022.05.12
  • Added R-tile and F-tile devices for VCCH specifications in the Absolute Maximum Rating for Intel Agilex Devices table.
  • Updated the F-Tile FGT Reference Clock Input Specifications for Intel Agilex Devices table.
    • Updated unit for VREFIN-DIFF-AC.
    • Updated VREFIN-IL-DC and VREFIN-IH-DC specifications.
    • Updated unit and specifications for TREF-RISE/FALL.
    • Added VREFIN-CM-AC and VREFIN-CM-DC specifications.
    • Updated parameter from PNREF-SSB to PNREF-SSB (156.25MHz).
  • Updated the F-Tile FGT Reference Clock Output Driver Specifications for Intel Agilex Devices table.
    • Updated TREF-RISE_OUT/FALL_OUT specifications.
    • Updated unit for VREFIN-DIFF-AC_OUT.
    • Added footnote to VREFIN-CM-OUT.
  • Updated the F-Tile FHT Transmitter Electrical Specifications table.
    • Removed TTX-DJ and TTX-RJ specifications.
    • Updated unit for Transmitter DC impedance.
  • Updated the F-Tile FGT Transmitter Electrical Specifications table.
    • Updated unit for VTX-DIFF-PKPK.
    • Removed VTX-EYE-PKPK specifications.
    • Updated description and unit for Transmitter DC impedance.
    • Updated ZRL-DIFF-DC specifications.
  • Updated unit for Receiver DC impedance in the F-Tile FHT Receiver Electrical Specifications table.
  • Updated the F-Tile FGT Receiver Electrical Specifications table.
    • Updated IINS-LOSS-56Gb/s, IINS-LOSS-30Gb/s, and IINS-LOSS-25Gb/s specifications.
    • Updated unit for Receiver DC impedance.
  • Updated the F-Tile FGT Electrical Compliance List table.
    • Removed JESD204A specifications.
    • Updated specifications for JESD204B, JESD204C, and HDMI protocols.
  • Updated tCF02ST0 specifications in the General Configuration Timing Specifications for Intel Agilex Devices table.
2022.04.15
  • Removed R31A package in the Data Sheet Status for Intel Agilex Devices (I-Series) table.
  • Updated footnote to VCCBAT in the Recommended Operating Conditions for Intel Agilex Devices table.
  • Changed the symbol from VCCR_CORE to VCCRCORE in the following tables:
    • Absolute Maximum Rating for Intel Agilex Devices
    • Recommended Operating Conditions for Intel Agilex Devices
2021.12.13 Updated the R-Tile Transmitter and Receiver Data Rate Performance for Intel Agilex Devices table.
2021.10.26
  • Updated the Data Sheet Status for Intel Agilex Devices (F-Series) table.
    • Updated status for AGF 012/014 R24A package.
    • Updated status for AGF 022/027 R25A package.
    • Added AGF 012/014 R24B package.
    • Added AGF 019/023 R25A, R24C, and R31C packages.
  • Added AGI 019/023 R18A and R31B packages in the Data Sheet Status for Intel Agilex Devices (I-Series) table.
  • Updated the Absolute Maximum Rating for Intel Agilex Devices table.
    • Updated footnotes for IOUT condition.
    • Changed symbol from VCCEH_FGT_GXF to VCCH_FGT_GXF.
  • Updated the Recommended Operating Conditions for Intel Agilex Devices table.
    • Added IBAT specifications.
    • Updated VI and VO specifications.
  • Added footnote to VCCCLK_GXP and VCCH_GXP in the P-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices table.
  • Updated the R-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices table.
    • Updated symbol from VCCEHT_GXR[L,R] to VCCH_GXR[L,R].
    • Updated symbol from VCCERT_GXR[L,R] to VCCRT_GXR[L,R].
    • Updated specifications for VCCH_GXR[L,R], VCCED_GXR[L,R], VCCCLK_GXR[L,R], and VCC_HSSI_GXR.
    • Added footnote to VCCH_GXR[L,R] and VCCCLK_GXR[L,R].
  • Updated descriptions in the Internal Weak Pull-Up Resistor section.
  • Added VIL (min) and VIH (max) in the Single-Ended I/O Standards Specifications for Intel Agilex Devices (for HPS and SDM I/O Banks) table.
  • Added footnotes to tREFPJ and tREFPN in the I/O PLL Specifications for Intel Agilex Devices table.
  • Updated descriptions in the Remote Temperature Diode Specifications section.
  • Added the following tables:
    • Remote Temperature Diode Specifications for Intel Agilex Devices (R-Tile TSD)
    • Remote Temperature Diode Specifications for Intel Agilex Devices (F-Tile TSD)
  • Removed the reference to rate support and combined the following tables into one table: Memory Standards Supported by Intel Agilex Devices
    • Memory Standards Supported by the Hard Memory Controller for Intel Agilex Devices
    • Memory Standards Supported by the Soft Memory Controller for Intel Agilex Devices
    • Memory Standards Supported by the HPS Hard Memory Controller for Intel Agilex Devices
  • Added footnote to FREF in the F-Tile FGT Reference Clock Input Specifications for Intel Agilex Devices table.
  • Updated ZREF-DIFF-DC_OUT and VREFIN-DIFF-AC_OUT descriptions in the F-Tile FGT Reference Clock Output Driver Specifications for Intel Agilex Devices table.
  • Updated the F-Tile FHT Transmitter Electrical Specifications table.
    • Updated TTX-DJ specification.
    • Removed NGPLL specification.
  • Updated the F-Tile FGT Transmitter Electrical Specifications table.
    • Updated VTX-DIFF-PKPK description.
    • Added VTX-EYE-PKPK specifications.
    • Removed NGPLL-PAM and NGPLL-NRZ specifications.
  • Updated the F-Tile FHT Receiver Electrical Specifications table.
    • Added VRX-MAX and VRX-MIN specifications.
    • Removed NGPLL specification.
  • Updated the F-Tile FGT Receiver Electrical Specifications table.
    • Added VRX-MIN specifications.
    • Updated footnote to VRX-MAX, VRX-CM-DC, and VIDLE-THRESH.
    • Removed NGPLL-PAM and NGPLL-NRZ specifications.
  • Updated the F-Tile FHT Electrical Compliance List table.
    • Removed IEEE 802.3cd 137/136, IEEE 802.3bj/bm 93, IEEE 802.3bj/bm 92, and IEEE 802.3by 111/110 specifications.
    • Updated the protocols for CEI 4.0/5.0 specification.
  • Updated the F-Tile FGT Electrical Compliance List table.
    • Updated specifications for SDI, JESD204A, JESD204B, JESD204C, Fiber Channel, Interlaken, and HDMI protocols.
    • Added specifications for GPON protocol.
  • Updated tCF02ST0 to add specifications when security features enabled in the General Configuration Timing Specifications for Intel Agilex Devices table.
  • Updated the description for Tdo in the AS Timing Parameters for Intel Agilex Devices table.
  • Updated the Configuration Bit Stream Sizes for Intel Agilex Devices table.
    • Added table description.
    • Added specifications for AGF 019, AGF 023, AGI 019, and AGI 023 devices.
    • Updated specifications for AGF 012, AGF 014, AGF 022, AGF 027, AGI 022, and AGI 027 devices.
  • Updated the Programmable IOE Delay for Intel Agilex Devices table.
    • Added Industrial grade and updated the fast model specifications.
    • Added –E1, –I1, –I2, and –I3V speed grades, and updated the slow model specifications.
2021.06.02
  • Updated the Data Sheet Status for Intel Agilex Devices (F-Series) table.
    • Removed R17A and R20A packages.
    • Added AGF 006 and AGF 008 devices for R24C package.
  • Added support for –E4X speed grade in the Intel Agilex Device Grades, Core Speed Grades, and Power Options Supported table.
  • Updated the Absolute Maximum Rating for Intel Agilex Devices table.
    • Updated the maximum specifications for VCCR_CORE and VCCA_PLL.
    • Removed VCCIO3V_GXB, VI (for VCCIO3V_GXB), VCC_HSSI_GXB, VCCH_GXB, VCCT_GXB, and VCCR_GXB specifications.
    • Added R-tile specifications: VCCEHT_GXR, VCCERT_GXR, VCCED_GXR, VCCE_PLL_GXR, VCCE_DTS_GXR, VCCCLK_GXR, VCCHFUSE_GXR, and VCC_HSSI_GXR.
    • Added F-tile specifications: VCCERT1_FHT_GXF, VCCERT2_FHT_GXF, VCCEHT_FHT_GXF, VCCERT_FGT_GXF, VCCEH_FGT_GXF, and VCCERT_GXF_COMBINE.
  • Updated the Recommended Operating Conditions for Intel Agilex Devices table.
    • Added specifications for –4X speed grade for VCC and VCCP.
    • Removed VCCH and VCCH_SDM specifications for H-tile and P-tile devices.
    • Removed VCCIO3V_GXB and VI (for VCCIO3V_GXB) specifications.
    • Added VCCH specifications for R-tile and F-tile devices.
    • Removed condition for VCCH_SDM.
  • Updated the HPS Power Supply Operating Conditions for Intel Agilex Devices table.
    • Added specifications for –4X speed grade for VCCL_HPS and VCCPLLDIG_HPS.
    • Added footnote for VCCL_HPS and VCCPLLDIG_HPS.
  • Updated specifications for 34-Ω and 40-Ω RS in the OCT Calibration Accuracy Specifications for Intel Agilex Devices (for GPIO Bank) table.
  • Updated VID and VICM(DC) specifications in the Differential I/O Standards Specifications for Intel Agilex Devices (for GPIO Bank) table.
  • Added specifications for –4X speed grade in the Clock Tree Performance for Intel Agilex Devices table.
  • Updated the I/O PLL Specifications for Intel Agilex Devices table.
    • Added specifications for –4X speed grade for fIN, fVCO, fOUT, and fOUT_EXT.
    • Updated tOUTDUTY specifications.
    • Updated footnote for tOUTPJ_DC, tOUTCCJ_DC, tOUTPJ_IO, and tOUTCCJ_IO.
  • Updated the DSP Block Performance Specifications for Intel Agilex Devices table.
    • Added specifications for –4X speed grade.
    • Added footnote for Fixed-point 18 × 19 multiplier adder summed with 36-bit input mode
    • Updated the modes as FP32 floating-point vector dot product and FP16 floating-point vector dot product.
    • Added the following modes:
      • Sum/sub of two FP16 multiplications with FP32 (addition/subtraction)
      • Sum/sub of two FP16 multiplications with accumulation (addition/subtraction)
  • Added specifications for –4X speed grade in the Memory Block Performance Specifications for Intel Agilex Devices table.
  • Added footnote to Sampling Rate in the Local Temperature Sensor Specifications for Intel Agilex Devices table.
  • Removed description on H-tile in the Remote Temperature Diode Specifications section.
  • Updated the Voltage Sensor Specifications for Intel Agilex Devices table.
    • Added footnote to Sampling Rate and Voltage sensor accuracy.
    • Removed Differential non-linearity (DNL) and Integral non-linearity (INL) specifications.
  • Updated the description for the Memory Standards Supported by the Soft Memory Controller for Intel Agilex Devices table.
  • Updated MPU frequency specifications in the Maximum HPS Clock Frequencies for Intel Agilex Devices table.
  • Added the HPS Cold Reset for Intel Agilex Devices table.
  • Updated Tsu specification in the SPI Master Timing Requirements for Intel Agilex Devices table.
  • Updated Tsuss and Thss specifications in the SPI Slave Timing Requirements for Intel Agilex Devices table.
  • Updated Td specifications in the HPS Secure Digital (SD)/MultiMediaCard (MMC) Timing Requirements for Intel Agilex Devices table.
  • Updated Th specification in the HPS USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) Low Pin Interface (ULPI) Timing Requirements for Intel Agilex Devices table.
  • Updated footnotes for THIGH and TLOW specifications in the HPS I2C Timing Requirements for Intel Agilex Devices table.
  • Updated Td specifications in the Trace Timing Requirements for Intel Agilex Devices table.
  • Updated tJPH specification in the HPS JTAG Timing Requirements for Intel Agilex Devices table.
  • Updated typical specifications in the HPS Programmable I/O Delay (Output Path) for Intel Agilex Device and HPS Programmable I/O Delay (Input Path) for Intel Agilex Device tables.
  • Added tST12CF0 and tST02CF1 specifications in the General Configuration Timing Specifications for Intel Agilex Devices table.
  • Added General Configuration Timing Diagram.
  • Updated the AS Timing Parameters for Intel Agilex Devices table.
    • Updated table description.
    • Updated Tclk, Tdcsfrs, Tdcslst, Tdo, Text_delay, and Tdcsb2b specifications.
    • Updated footnote for Text_delay.
  • Updated tADH specification in the Avalon-ST Timing Parameters for x8, ×16, and ×32 Configurations in Intel Agilex Devices table.
  • Updated the Configuration Bit Stream Sizes for Intel Agilex Devices table.
    • Removed AGF 004 device.
    • Updated specifications for AGF 006 device.
  • Added R-tile and F-tile specifications. Added the following tables/sections:
    • R-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices table
    • F-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices table
    • R-Tile Transceiver Performance Specifications section
    • F-Tile Transceiver Performance Specifications section
  • Removed H-Tile specifications. The following tables/section are removed:
    • H-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices
    • Remote Temperature Diode Specifications for Intel Agilex Devices (H-Tile TSD)
    • H-Tile Transceiver Performance Specifications
  • Removed the following tables for 3 V I/O banks:
    • Maximum Allowed Overshoot During Transitions for Intel Agilex Devices (for 3 V I/O Bank)
    • I/O Pin Leakage Current for Intel Agilex Devices (for 3 V I/O Bank)
    • Bus Hold Parameters for Intel Agilex Devices (for 3 V I/O Bank)
    • OCT Without Calibration Resistance Tolerance Specifications for Intel Agilex Devices (for 3 V I/O Bank)
    • Pin Capacitance for Intel Agilex Devices (for 3 V I/O Bank)
    • Internal Weak Pull-Up Resistor Values for Intel Agilex Devices (for 3 V I/O Bank)
    • Single-Ended I/O Standards Specifications for Intel Agilex Devices (for 3 V I/O Bank)
2021.01.07
  • Updated the Data Sheet Status for Intel Agilex Devices tables.
  • Updated table title from Intel Agilex Device Grades and Speed Grades Supported to Intel Agilex Device Grades, Core Speed Grades, and Power Options Supported.
  • Added VCCIO3V_GXB, VI (for VCCIO3V_GXB), VCC_HSSI_GXB, VCCH_GXB, VCCT_GXB, and VCCR_GXB specifications in the Absolute Maximum Rating for Intel Agilex Devices table.
  • Updated the description in the Maximum Allowed Overshoot and Undershoot Voltage section.
  • Updated the figure title to Intel Agilex Devices Overshoot Duration Example (for 1.2 V GPIO Bank at VCCIO_PIO = 1.26 V).
  • Updated the Recommended Operating Conditions for Intel Agilex Devices table.
    • Updated VCC and VCCP specifications.
    • Updated description for VCCH.
    • Added VCCH and VCCH_SDM specifications for H-tile and P-tile devices.
    • Updated note to VCCBAT.
    • Added VCCIO3V_GXB and VI (for VCCIO3V_GXB) specifications.
    • Updated the minimum specification for tRAMP.
  • Added the H-Tile Transceiver Power Supply Operating Conditions for Intel Agilex Devices table.
  • Updated VCCL_HPS and VCCPLLDIG_HPS specifications in the HPS Power Supply Operating Conditions for Intel Agilex Devices table.
  • Updated the specifications in the I/O Pin Leakage Current for Intel Agilex Devices (For GPIO Bank) table.
  • Updated the specifications in the Bus Hold Parameters for Intel Agilex Devices (For GPIO Bank) table.
  • Added specifications for 100-Ω RD for VCCIO_PIO = 1.2 V in the OCT Without Calibration Resistance Tolerance Specifications for Intel Agilex Devices (For GPIO Bank) table.
  • Updated the specifications in the Pin Capacitance for Intel Agilex Devices table.
  • Updated the specifications in the Internal Weak Pull-Up Resistor Values for Intel Agilex Devices (For GPIO Bank) table.
  • Updated the Single-Ended I/O Standards Specifications for Intel Agilex Devices (For GPIO Bank) table.
    • Removed note to 1.2 V LVCMOS in the Single-Ended I/O Standards Specifications for Intel Agilex Devices (for GPIO Bank) table.
    • Added VOL and VOH specifications.
  • Added the following tables for HPS, SDM, and 3 V I/O banks:
    • Maximum Allowed Overshoot During Transitions for Intel Agilex Devices (for 3 V I/O Bank)
    • I/O Pin Leakage Current for Intel Agilex Devices (for HPS and SDM I/O Bank)
    • I/O Pin Leakage Current for Intel Agilex Devices (for 3 V I/O Bank)
    • Bus Hold Parameters for Intel Agilex Devices (for 3 V I/O Bank)
    • OCT Without Calibration Resistance Tolerance Specifications for Intel Agilex Devices (for 3 V I/O Bank)
    • Pin Capacitance for Intel Agilex Devices (for 3 V I/O Bank)
    • Internal Weak Pull-Up and Weak Pull-Down Resistor Values for Intel Agilex Devices (for HPS and SDM I/O Banks)
    • Internal Weak Pull-Up Resistor Values for Intel Agilex Devices (for 3 V I/O Bank)
    • Hysteresis Specifications for Schmitt Trigger Input for Intel Agilex Devices (for HPS I/O Bank)
    • Single-Ended I/O Standards Specifications for Intel Agilex Devices (for HPS and SDM I/O Banks)
    • Single-Ended I/O Standards Specifications for Intel Agilex Devices (for 3 V I/O Bank)
  • Updated specification for –1 speed grade in the Clock Tree Performance for Intel Agilex Devices table.
  • Updated the I/O PLL Specifications for Intel Agilex Devices table.
    • Updated fIN, fVCO, and fOUT specifications for –4F speed grade.
    • Updated fOUT_EXT specifications for –2, –3, and –4 speed grades.
    • Added tINCCJ specifications.
    • Added note to tOUTPJ_DC, tOUTCCJ_DC, tOUTPJ_IO, and tOUTCCJ_IO.
    • Updated condition for tOUTPJ_DC, tOUTCCJ_DC, tOUTPJ_IO, tOUTCCJ_IO, and tCASC_OUTPJ_DC.
  • Updated the description in the Remote Temperature Diode Specifications section.
  • Updated Ibias, Vbias, and diode ideality factor specifications in the Remote Temperature Diode Specifications for Intel Agilex Devices (E-Tile TSD) table.
  • Added the Remote Temperature Diode Specifications for Intel Agilex Devices (H-Tile TSD) table.
  • Updated the Voltage Sensor Specifications for Intel Agilex Devices table.
    • Updated voltage sensor accuracy Vin range and specifications.
    • Updated Unipolar Input Mode specifications.
  • Updated tx Jitter for data rate 600 Mbps – 1.6 Gbps in the LVDS SERDES Specifications for Intel Agilex Devices table.
  • Updated the jitter amplitude in the LVDS SERDES Soft-CDR Sinusoidal Jitter Tolerance Specifications for a Data Rate Equal to 1.6 Gbps diagram.
  • Updated the sinusoidal jitter for F3 and F4 in the LVDS SERDES Soft-CDR Sinusoidal Jitter Mask Values for a Data Rate Equal to 1.6 Gbps table.
  • Removed RLDRAM 3 specifications from the Memory Standards Supported by the Soft Memory Controller for Intel Agilex Devices table.
  • Updated the E-Tile Receiver Specifications table.
    • Updated absolute VMAX for a receiver pin specifications.
    • Changed from VICM (AC coupled) to VCM (Internal AC coupled) and updated the specifications.
  • Updated the P-Tile PLLA Performance table.
    • Added PLL bandwidth (BWTX-PKG_PLL1) and PLL peaking (PKGTX-PLL1) specifications for PCIe 5.0 GT/s.
    • Updated PLL peaking (PKGTX-PLL2) specifications.
    • Added note on PLL bandwidth and PLL peaking.
  • Updated the P-Tile PLLB Performance table.
    • Added PLL bandwidth (BWTX-PKG_PLL2) and PLL peaking (PKGTX-PLL2) specifications.
    • Added note on PLL bandwidth and PLL peaking.
  • Updated the P-Tile Reference Clock Specifications table.
    • Updated notes to Input reference clock frequency and TCCJITTER.
    • Added conditions for Rising edge rate, Falling edge rate, Duty cycle, VICM, TCCJITTER, and TSSC-MAX-PERIOD-SLEW parameters.
    • Updated spread-spectrum downspread, absolute VMAX, and absolute VMIN specifications.
  • Added condition for differential on-chip termination resistors parameter in the P-Tile Transmitter Specifications table.
  • Updated the P-Tile Receiver Specifications table.
    • Updated VID (diff p-p) specifications for PCIe 16.0 GT/s.
    • Removed VICM (AC coupled) specifications.
    • Added RREF specifications.
  • Added H-Tile Transceiver Performance Specifications section.
  • Updated fixed VCCL_HPS and MPU frequency for –1 speed grade in the Maximum HPS Clock Frequencies for Intel Agilex Devices table.
  • Updated the internal oscillator frequency in the HPS Internal Oscillator Frequency for Intel Agilex Devices table.
  • Added the HPS JTAG Timing Diagram.
  • Updated the HPS Programmable I/O Delay (Output Path) for Intel Agilex Device and HPS Programmable I/O Delay (Input Path) for Intel Agilex Device tables.
  • Removed note to tCF12ST1 in the General Configuration Timing Specifications for Intel Agilex Devices table.
  • Updated the POR Delay Specification for Intel Agilex Devices table.
  • Updated the description for clock input peak-to-peak period jitter tolerance parameter in the External Configuration Clock Source (OSC_CLK_1) Clock Input Requirements table.
  • Added notes to tJPSU (TDI), tJPSU (TMS), tJPH, and tJPCO in the JTAG Timing Parameters and Values for Intel Agilex Devices table.
  • Updated the AS Timing Parameters for Intel Agilex Devices table.
    • Updated the note to Tdo.
    • Updated Tdcsb2b specification.
  • Updated the AS Configuration Serial Input Timing Diagram to include Tdcsb2b.
  • Removed Maximum Configuration Time Estimation specifications.
2020.06.30
  • Updated the Recommended Operating Conditions for Intel Agilex Devices table.
    • Added note to VCCIO_PIO_SDM.
    • Removed the note on HPS_PORSEL from tRAMP. HPS_PORSEL pin is not available for Intel Agilex devices.
  • Added note to Text_delay in the AS Timing Parameters for Intel Agilex Devices table.
  • Removed SD/MMC configuration mode specifications in the following tables:
    • POR Delay Specification for Intel Agilex Devices
    • Maximum Configuration Time Estimation for Intel Agilex Devices
2020.05.14 Updated VCCFUSEWR_SDM specifications in the Recommended Operating Conditions for Intel Agilex Devices table.
2020.03.18
  • Added the Absolute Maximum Rating for Intel Agilex Devices table.
  • Added Maximum Allowed Overshoot and Undershoot Voltage section.
  • Updated the Recommended Operating Conditions for Intel Agilex Devices table.
    • Updated the typical values for VCC and VCCP.
    • Added VCCR_CORE specifications.
    • Updated description for VCCPT and VCCIO_PIO_SDM.
    • Updated VCCFUSEWR_SDM and VI specifications.
    • Updated VCCA_PLL specifications and description.
    • Added a note for TJ minimum specifications for Industrial.
    • Updated tRAMP minimum specification.
  • Updated the E-Tile Transceiver Power Supply Operating Conditions table.
    • Updated VCCCLK_GXE for maximum DC level.
    • Updated VCCCLK_GXE for recommended AC transient level.
    • Updated wording for all recommended DC values from % of DC level to % of Vnominal.
  • Updated wording for all recommended DC values from % of DC level to % of Vnominal in the P-Tile Transceiver Power Supply Operating Conditions.
  • Updated the E-Tile Transmitter and Receiver Data Rate Performance Specifications table with the transceiver speed grades for the NRZ and PAM4 supported data rates.
  • Updated the transmitter differential output voltage peak-to-peak typical value in the E-Tile Transmitter Specifications table.
  • Updated the E-tile Receiver Specifications table:
    • Added the absolute Vmax for a receiver pin specification
    • Added the maximum peak-to-peak differential input voltage VID (diff p-p) before/after device configuration specification
    • Added VICM (AC coupled) specification
    • Removed the electrical idle detection voltage specification
  • Updated P-Tile Transceiver Performance:
    • Added supported data rate for Gen1, Gen 2, Gen 3, and Gen 4 in the P-Tile Transmitter and Receiver Data Rate Performance table.
    • Removed the maximum VCO frequency value and replaced it with a typical value in the P-Tile PLLA Performance table.
    • Removed the maximum VCO frequency value and replaced it with a typical value in the P-Tile PLLB Performance table.
  • Updated P-Tile Transmitter Specifications:
    • Added PCIe condition for Supported I/O Standards.
    • Removed VOCM (AC Coupled).
  • Updated P-Tile Receiver Specifications:
    • Added PCIe condition for Supported I/O Standards.
    • Added PCIe 8.0 GT/s and 16.0 GT/s specifications for the peak-to-peak differential input voltage VID (diff p-p) and added corresponding notes.
    • Updated RESREF specification. Added a note to the RESREF specification.
  • Updated VCCL_HPS and VCCPLLDIG_HPS specifications for SmartVID in the HPS Power Supply Operating Conditions for Intel Agilex Devices table.
  • Changed Early Power Estimator (EPE) to Intel FPGA Power and Thermal Calculator.
  • Added a note to 1.2 V LVCMOS in the Single-Ended I/O Standards Specifications for Intel Agilex Devices table.
  • Added a note in the Single-Ended SSTL, HSTL, HSUL, and POD I/O Standards Signal Specifications for Intel Agilex Devices table.
  • Updated the Differential I/O Standards Specifications for Intel Agilex Devices table.
    • Updated I/O standard name from "1.5 V True Differential Signaling" to "True Differential Signaling (Transmitter & Receiver)".
    • Added specifications for True Differential Signaling (Receiver only).
    • Updated note to True Differential Signaling.
  • Updated the I/O PLL Specifications for Intel Agilex Devices table.
    • Added notes for tFCOMP, tOUTPJ_DC, and tOUTCCJ_DC.
    • Removed tINCCJ specifications.
    • Added tREFPJ and tREFPN specifications.
    • Updated tOUTPJ_DC, tOUTCCJ_DC, tOUTPJ_IO, tOUTCCJ_IO, and tCASC_OUTPJ_DC specifications.
  • Added a note for fixed-point 27 × 27 multiplication mode in the DSP Block Performance Specifications for Intel Agilex Devices table.
  • Updated the Memory Block Performance Specifications for Intel Agilex Devices table.
    • Updated the specifications for MLAB memory.
    • Updated the specifications for M20K block and added low power (LP) specifications.
  • Updated the specifications in the Remote Temperature Diode Specifications for Intel Agilex Devices (Core Fabric TSD) table.
  • Added the Remote Temperature Diode Specifications for Intel Agilex Devices (P-Tile TSD) table.
  • Updated the LVDS SERDES Specifications for Intel Agilex Devices table.
    • Updated the tx Jitter - True Differential I/O Standards specifications for –4 speed grade.
    • Removed global, regional, or local in clock routing resource.
  • Updated the DPA Lock Time Specifications for Intel Agilex Devices table.
    • Updated the description of the table.
    • Updated the maximum data transition from 960 to 768.
  • Updated the jitter requirements in the Memory Output Clock Jitter Specifications section.
  • Updated the specifications in the Maximum HPS Clock Frequencies for Intel Agilex Devices table.
  • Updated the HPS Programmable I/O Delay (Output Path) for Intel Agilex Device and HPS Programmable I/O Delay (Input Path) for Intel Agilex Device tables.
  • Updated the following diagrams:
    • USB ULPI Timing Diagram
    • RGMII TX Timing Diagram
    • RMII TX Timing Diagram
    • RMII RX Timing Diagram
  • Updated tST0 and tCD2UM specifications in the General Configuration Timing Specifications for Intel Agilex Devices table.
  • Added notes to Tclk and Tdo specifications in the AS Timing Parameters for Intel Agilex Devices table.
  • Updated tADSU and tAVSU specifications in the Avalon-ST Timing Parameters for ×8, ×16, and ×32 Configurations in Intel Agilex Devices table.
  • Added the following tables:
    • Configuration Bit Stream Sizes for Intel Agilex Devices
    • Maximum Configuration Time Estimation for Intel Agilex Devices
    • Programmable IOE Delay for Intel Agilex Devices
2019.12.18 Updated the I/O PLL Specifications for Intel Agilex Devices table.
  • Removed scanclk from fDYCONFIGCLK parameter.
  • Corrected the maximum specification for fDYCONFIGCLK from 200 MHz to 100 MHz.
2019.04.02 Initial release.