DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022

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5.8.5. Transceiver Reconfiguration Interface

You can reconfigure the transceiver to accept single reference clock. The single reference clock is a 135 MHz clock for all DP1.4 bit rates: RBR, HBR, HBR2, and HBR3. DP2.0 uses the reference clock at 100MHz for the UHBR10 data rate.

During run-time, you can reconfigure the transceiver to operate in either one of the bit rates by changing TX PLL divide ratio.

When the IP makes a request, the tx_reconfig_req port goes high. The user logic asserts tx_reconfig_ack and then reconfigures the transceiver. During reconfiguration, the user logic holds tx_reconfig_busy high. The user logic drives it low when reconfiguration completes.

Note: The transceiver requires a reconfiguration controller. Reset the transceiver to a default state upon power-up.