DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022
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10.3.2. DPTX_PRE_VOLT1/DPTX_REG_TXFFE1

These ports drive the respective tx_vod, tx_emp ports (8B/10B channel coding), and tx_reconfig_ffe1 (128B/132B channel coding).

Address: 0x0011

Direction: RW

Reset: 0x00000000

Table 80.  DPTX_PRE_VOLT1/DPTX_REG_TXFFE1 Bits

Bit

Bit Name

Function

31:8

Unused

7:4 TX_FFE1

128B/132B Channel Coding:

Tx FFE Preset on lane 1

3:2

PRE1

8B/10B Channel Coding:

Pre-emphasis output on lane 1

1:0

VOLT1

8B/10B Channel Coding:

Voltage swing output on lane 1