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- 4.1. DisplayPort Intel® FPGA IP Hardware Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-Tile Devices
5.8.1. Controller Interface
The controller interface allows you to control the source from an external or on-chip controller, such as the Nios II processor.
The controller can control the DisplayPort link parameters and the AUX channel controller.
The AUX channel controller interface works with a simple serial-port-type peripheral that operates in a polled mode. Because the DisplayPort AUX protocol is a master-slave interface, the DisplayPort source (the master) starts a transaction by sending a request and then waits for a reply from the attached sink.
The controller interface includes a single interrupt source. The interrupt notifies the controller of an HPD signal state change. Your system can interrogate the DPTX_TX_STATUS register to determine the cause of the interrupt. Writing to the DPTX_TX_STATUS register clears the pending interrupt event.
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