DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022

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6. DisplayPort Sink

The DisplayPort sink consists of a DisplayPort decoder block, a transceiver management block, a controller interface block, and an HDCP interface block with an Avalon® memory-mapped interface for connecting with an embedded controller such as the Nios II processor.

Figure 28. DisplayPort Sink Top-Level Block Diagram
Figure 29. DisplayPort 1.4 Sink Functional Block Diagram

The DP1.4 device transceiver sends 20-bit (dual symbol) or 40-bit (quad symbol) parallel DisplayPort data to the sink. Each data lane is clocked in to the IP by its own respective clock output from the transceiver. Inside the sink, the four independent clock domains are synchronized to the lane 0 clock. Then, the IP performs the following actions:

  1. The IP aligns the data stream and performs 8B/10B decoding.
  2. The IP deskews the data and then descrambles it.
  3. The IP splits the unscrambled data stream into parallel paths.
    1. The SS decoder block performs secondary stream decoding, which the core transfers into the rx_ss_clk domain through a DCFIFO.
    2. The main data path extracts all pixel data from the incoming stream. Then, the gearbox block resamples the pixel data into the current bit-per-pixel data width. Next, the IP core crosses the pixel data into the rxN_vid_clk domain through a DCFIFO. Finally, the IP steers the data into a single, dual, or quad pixel data stream.
    3. MSA decode path.
    4. Video decode path.