DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.3.5. DisplayPort Link Training Flow

Upon Hot Plug detection, the DisplayPort source configures the link through link training.

The DisplayPort source device accesses the sink’s DPCD register block through the AUX channel to determine the sink’s capability and status and initiate the Link Training command.

The sequence below describes the Link Training flow after HPD assertion:
  1. The DisplayPort source reads the DPCD Capabilities fields offset 0x00000 – 0x0000D to determine the sink device’s capability.
  2. The source writes to the Link Configuration field offset 0x00100 – 0x00101 to configure the Link Bandwidth and Lane Count according to the sink device’s requirements.
After Link Configuration, the source initiates Link Training Pattern Sequence 1.
  1. The source writes to offset 0x00102 to select Training Pattern 1 and Disable Scrambling. The source sends Training Pattern 1 through the Main Link at the same time.
  2. The source writes to offset 0x00103 – 0x00106 to configure the Link Training Control for every lane.
  3. The source reads from offset 0x0000E for TRAINING_AUX_RD_INTERVAL value.
  4. The source waits for a period of time specified in TRAINING_AUX_RD_INTERVAL before it reads the Link Status (0x00202 – 0x00207) from the sink device.
  5. If the clock recovery core (CR_DONE) fails in one or more lanes:
    • The source checks for the Link Driver setting adjust request (0x00206 – 0x00207) and responds accordingly.
    • In the same Link Driver setting, if the source has already repeated Training Pattern Sequence 1 for 5 times, the source will lower the Link Bandwidth (from HBR2 to HBR to RBR) in offset 0x00100 and starts back at Step 1.
    • If the Link Bandwidth is already in the lowest rate (RBR), then Link Training fails.
For Link Training Pattern Sequence 2:
  1. The source writes to offset 0x00102 to select Training Pattern 2 and Disable Scrambling. The source sends Training Pattern 2 through the Main Link at the same time.
  2. The source writes to offset 0x00103 – 0x00106 to configure the Link Training Control for every lane.
  3. The source reads from offset 0x0000E for TRAINING_AUX_RD_INTERVAL value.
  4. The source waits for a period of time specified in TRAINING_AUX_RD_INTERVAL before it reads the Link Status (0x00202 – 0x00207) from the sink device.
  5. If CR_DONE (0x00202) fails in one or more lanes, abort Training Pattern Sequence 2, and restart Training Pattern Sequence 1.
  6. If CR_DONE passes all lanes, check if the following operations fail or pass:
    • CHANNEL_EQ_DONE
    • SYMBOL_LOCKED
    • INTERLANE_ALIGN_DONE
  7. If CHANNEL_EQ_DONE, SYMBOL_LOCKED or INTERLANE_ALIGN_DONE fails in one or more lanes:
    • The source checks for the Link Driver setting adjust request (0x00206 – 0x00207) and responds accordingly.
    • In the same Link Driver setting, if the source has already repeated Training Pattern Sequence 2 for 5 times, the source will lower the Link Bandwidth (from HBR2 to HBR to RBR) in offset 0x00100, aborts Training Pattern Sequence 2, and restarts Link Training Pattern Sequence 1.
    • If the Link Bandwidth is already in the lowest rate (RBR), then Link Training fails.
  8. If Training Pattern Sequence 2 passes, then Link Training completes.
  9. The source writes to offset 0x00102 to disable Link Training.
    Note: If both DisplayPort source and sink support HBR2, replace Training Pattern Sequence 2 with Training Pattern Sequence 3.

Did you find the information on this page useful?

Characters remaining:

Feedback Message