DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022
Public

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10.2.9. DPTX0_MSA_VSP

Address: 0x0028

Direction: RO

Reset: 0x00000000

Note: This register is RO if TX_VIDEO_IM_ENABLE = 0 and RW if TX_VIDEO_IM_ENABLE = 1.
Table 71.  DPTX0_MSA_VSP Bits

Bit

Bit Name

Function

31:1

Unused

0

VSP

Main stream attribute vertical sync polarity

  • 0 = Positive
  • 1 = Negative