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- 4.1. DisplayPort Intel® FPGA IP Hardware Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-Tile Devices
Target Average Time Slots
Target Average Time Slots for Stream 3
Target Average Time Slots for Stream 2
Target Average Time Slots for Stream 1
Target Average Time Slots for Stream 0
TAVG_TS x is expressed as the fractional part of the number of time slots per MTU occupied by Stream x times 64; assuming the allocated time slots are the ceiling of this number. For example, if 4.7 time slots/MTU are occupied (5 time slots/MTU are allocated in the VCP ID table.
TAVG_TS x = CEIL (FRAC (4.7)*64) = CEIL (0.7*64) = 45
The achieved precision for Target Average Time Slots regulation is 1/64 = 0.015625.
If TAVG_TS x is set to a value greater than 63, VCP fill is sent to each allocated time slot.
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