DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022
Public

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9.31. btc_dptx_fast_link_training

Prototype:

int btc_dptx_fast_link_training( 
   BYTE tx_idx,
   unsigned int link_rate, 
   unsigned int lane_count, 
   unsigned int volt_swing, 
   unsigned int pre_emph, 
   unsigned int new_cfg)

Thread-safe:

No

Available from ISR:

Yes

Include:

< btc_dptx_syslib.h >

Return:

0 = success, 1 = fail

Parameters:

  • tx_idx—Source instance index (0 - 3)
  • link_rate—Link rate: 0x06 = 1.62 Gbps; 0x0A = 2.70 Gbps; ox14 = 5.40 Gbps
  • lane_count—1, 2, or 4
  • volt_swing—0, 1, 2, or 3
  • pre_emph—0, 1, 2, or 3
  • new_cfg—0 = ignore the other parameters; 1 = use provided parameters

Description:

This function performs fast link training with the connected DisplayPort sink. When performing fast link training, the IP outputs training pattern 1 for 1 ms followed by training pattern 2 for 1 ms. The function returns a 1 if link training fails or if the DPCD flag NO_AUX_HANDSHAKE_LINK_TRAINING = 0 (at location 00103h).

  • If new_cfg = 1, the IP updates the sink’s DPCD with the provided link_rate and lane_count, sets its own transceiver with the provided volt_swing and pre_emph, and then performs fast link training.
  • If new_cfg = 0, the IP uses the current transceiver setting, link rate, and lane count, and performs fast link training.

Example:

btc_dptx_fast_link_training(0, 0x0A, 4, 1, 0, 1);