DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022
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8. DisplayPort Intel® FPGA IP Simulation Example

The DisplayPort simulation example allows you to evaluate the functionality of the DisplayPort Intel® FPGA IP and provides a starting point for you to create your own simulation. This example targets the ModelSim* SE simulator.

The simulation example instantiates the DisplayPort Intel® FPGA IP with default settings, TX and RX enabled, and 8 bits per color. The core has the Support CTS test automation parameter turned on, which is required for the simulation to pass.

The test harness instantiates the design under test (DUT) and a VGA driver. It also generates the clocks and top-level stimulus. The design manipulates the tx_mgmt interface in the main loop to establish a link and send several frames of video data. The test harness checks that the sent data’s CRC matches the received data’s CRC for three frames.

Figure 42. Simulation Example Block Diagram for Arria V, Cyclone V, and Stratix V DevicesThe files are named <prefix>_<name>.<extension> where <prefix> represents the device (av for Arria V devices, cv for Cyclone V devices, and sv for Stratix V devices).