DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022
Public

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10.9. Source-Supported DPCD Locations

The following table describes the DPCD locations (or location groups) that are supported in DisplayPort source instantiations.

Table 130.  DPCD Locations
Location Name Address
DPCD_REV 0x0000
MAX_LINK_RATE 0x0001
MAX_LANE_COUNT 0x0002
TRAINING_AUX_RD_INTERVAL 0x000E
MST_CAP 0x0021
GUID 0x0030
LINK_BW_SET 0x0100
LANE_COUNT_SET 0x0101
TRAINING_PATTERN_SET 0x0102
TRAINING_LANE0_SET 0x0103
TRAINING_LANE1_SET 0x0104
TRAINING_LANE2_SET 0x0105
TRAINING_LANE3_SET 0x0106
DOWNSPREAD_CTRL 0x0107
MSTM_CTRL 0x0111
PAYLOAD_ALLOCATE_SET 0x01C0
PAYLOAD_ALLOCATE_START_TIME_SLOT 0x01C1
PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x01C2
SINK_COUNT 0x0200
DEVICE_SERVICE_IRQ_VECTOR 0x0201
LANE0_1_STATUS 0x0202
LANE2_3_STATUS 0x0203
LANE_ALIGN_STATUS_UPDATED 0x0204
SINK_STATUS 0x0205
ADJUST_REQUEST_LANE0_1 0x0206
ADJUST_REQUEST_LANE2_3 0x0207
SYMBOL_ERROR_COUNT_LANE0 0x0210
SYMBOL_ERROR_COUNT_LANE1 0x0212
SYMBOL_ERROR_COUNT_LANE2 0x0214
SYMBOL_ERROR_COUNT_LANE3 0x0216
TEST_REQUEST 0x0218
TEST_LINK_RATE 0x0219
TEST_LANE_COUNT 0x0220
PHY_TEST_PATTERN 0x0248
TEST_80BIT_CUSTOM_PATTERN (0x0250 to 0x0259) 0x0250
TEST_RESPONSE 0x0260
TEST_EDID_CHECKSUM 0x0261
PAYLOAD_TABLE_UPDATE_STATUS 0x02C0
VC_PAYLOAD_ID_SLOT_1 (0x02C1 to 0x02FF) 0x02C1
SET_POWER_STATE 0x0600
DOWN_REQ (0x1000 to 0x102F) 0x1000
UP_REP (0x1200 to 0x122F) 0x1200
DOWN_REP (0x1400 to 0x142F) 0x1400
UP_REQ (0x1600 to 0x162F) 0x1600

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