DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022
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11.3.2. DPRX_BER_CNTI1

Bit-error counter register for lane 2 and lane 3.

Address: 0x0007

Direction: RO

Reset: 0x00000000

Table 139.  DPRX_BER_CNTI1 Bits

Bit

Bit Name

Function

31

Unused

30:16

CNT3

Symbol error counter for lane 3

15

Unused

14:0

CNT2

Symbol error counter for lane 2

These registers are meant for internal use and are not exposed in the DPCD.