DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.8.3.2. Video Interface (TX Video IM Enable = 1)

If you enable the video image interface feature, the core uses the video image interface (txN_video_in_im).

The txN_video_in_im ports replace the txN_video_in ports when you turn on the TX Video IM Enable parameter. The txN_video_in_im ports (N = 0 to 3) transmit video data when either the horizontal/vertical syncs or the exact pixel clock is not available. The streams need synchronization pulses at the start and end of active lines and active frames.

The timing diagram below illustrates the behavior of the ports when TX_PIXELS_PER_CLOCK = 4, TX_VIDEO_BPC = 10, and line length = 16 pixels.

Figure 20. Video Image Interface Ports Timing Diagram
  • You specify the data input width through the Maximum video input color depth parameter. The core uses the same output port to transfer both RGB and YCbCr data in either 4:4:4, 4:2:2, or 4:2:0 color format.
  • The data organization and pixel ordering of the txN_im_data ports are identical to the ones of the txN_vid_data signals.
  • When you configure the Pixel input mode parameter to Dual or Quad, the IP sends two or four pixels in parallel respectively.
  • The txN_im_valid signal is widened to support video horizontal resolutions not divisible by two or four. For example, if TX_PIXELS_PER_CLOCK = 2, txN_im_valid[0] must assert when pixel N belongs to active video and txN_im_valid[1] must assert when pixel N+1 belongs to active video.
  • For interlaced video, the core samples txN_im_field when txN_im_sof asserts. When txN_im_field asserts, it marks txN_im_data as belonging to the top field.
  • The frequency of the txN_im_clk signal must be equal to or higher than the frequency of the maximum video pixel clock to be transmitted divided by the pixel input mode.
  • Not all clock cycles need to contain valid (active) pixel data; only those indicated by the assertion of txN_im_valid.
  • The txN_video_in_im ports support the Adaptive Sync feature.
The source core measures only some of the MSA parameters from the incoming video signal:
  • MVID
  • HWIDTH
  • VHEIGHT VSP and VSW

The GPU MSA registers for the remaining MSA parameters are Read/Write and you can set the value for these parameters:

  • HTOTAL and VTOTAL
  • HSP and HSW
  • HSTART and VSTART
Note: The source core needs only HTOTAL because the core calculates the value of MVID from the interval time between txN_im_sol pulses and the amount of pixels accounted for. The source core ignores the rest of the MSA parameters and forwards to the connected sink.

Did you find the information on this page useful?

Characters remaining:

Feedback Message