DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022

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6.6.7. Transceiver Reconfiguration Interface

You can reconfigure the transceiver to accept a single reference clock of 135 MHz for all DP1.4 bit rates: RBR, HBR, HBR2, and HBR3. DP2.0 bit rate at UHBR10 uses reference clock at 100 MHz.

During run-time, you can reconfigure the transceiver to operate in either one of the bit rates by changing RX CDR PLLs divider ratio.

When the IP makes a request, the rx_reconfig_req port goes high. The user logic asserts rx_reconfig_ack, and then reconfigures the transceiver. During reconfiguration, the user logic holds rx_reconfig_busy high. The user logic drives it low when reconfiguration completes.

Note: The transceiver requires a reconfiguration controller. Reset the transceiver to a default state upon power-up.