DisplayPort Intel® FPGA IP User Guide

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ID 683273
Date 1/24/2022
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Quick Reference 2. About This IP 3. Getting Started 4. DisplayPort Intel® FPGA IP Hardware Design Examples 5. DisplayPort Source 6. DisplayPort Sink 7. DisplayPort Intel® FPGA IP Parameters 8. DisplayPort Intel® FPGA IP Simulation Example 9. DisplayPort API Reference 10. DisplayPort Source Register Map and DPCD Locations 11. DisplayPort Sink Register Map and DPCD Locations 12. DisplayPort Intel® FPGA IP User Guide Archives 13. Document Revision History for the DisplayPort Intel® FPGA IP User Guide
1. DisplayPort Intel® FPGA IP Quick Reference x
1.1. DisplayPort Terms and Acronyms
2. About This IP x
2.1. Release Information 2.2. Device Family Support 2.3. IP Core Verification 2.4. Performance and Resource Utilization
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying IP Parameters and Options 3.3. Simulating the Design 3.4. Compiling the Full Design and Programming the FPGA 3.5. Calculating Video Bandwidth and Recovered Pixel Clock Frequency
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.3. Simulating the Design x
3.3.1. Simulating with the ModelSim Simulator
4. DisplayPort Intel® FPGA IP Hardware Design Examples x
4.1. DisplayPort Intel® FPGA IP Hardware Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-Tile Devices 4.2. HDCP Over DisplayPort Design Example for Intel® Arria® 10 and Intel® Stratix® 10 Devices 4.3. DisplayPort Intel® FPGA IP Hardware Design Examples for Arria V, Cyclone V, and Stratix V Devices
4.3. DisplayPort Intel® FPGA IP Hardware Design Examples for Arria V, Cyclone V, and Stratix V Devices x
4.3.1. Clock Recovery Core 4.3.2. Transceiver and Clocking 4.3.3. Required Hardware 4.3.4. Design Walkthrough 4.3.5. DisplayPort Link Training Flow 4.3.6. DisplayPort Post Link Training Adjust Request Flow (LQA) 4.3.7. DisplayPort MST Source User Application
4.3.1. Clock Recovery Core x
4.3.1.1. Clock Recovery Core Parameters 4.3.1.2. Clock Recovery Interface
4.3.1.2. Clock Recovery Interface x
4.3.1.2.1. Video Input Port
4.3.4. Design Walkthrough x
4.3.4.1. Set Up the Hardware 4.3.4.2. Copy the Design Files to Your Working Directory 4.3.4.3. Build the FPGA Design 4.3.4.4. Load and Run the Software 4.3.4.5. View the Results
5. DisplayPort Source x
5.1. IP to Transceiver Parallel Data Interface Width 5.2. Main Data Path 5.3. Controller Interface 5.4. Sideband Channel 5.5. Source Embedded DisplayPort (eDP) Support 5.6. HDCP 1.3 TX Architecture 5.7. HDCP 2.3 TX Architecture 5.8. Source Interfaces 5.9. Source Clock Tree
5.2. Main Data Path x
5.2.1. Video Packetizer Path 5.2.2. Video Geometry Measurement Path 5.2.3. Audio and Secondary Stream Encoder Path 5.2.4. Training and Link Quality Patterns Generator
5.2.4. Training and Link Quality Patterns Generator x
5.2.4.1. DP1.4 (8B/10B Channel Coding) 5.2.4.2. DP2.0 (128B/132B Channel Coding)
5.8. Source Interfaces x
5.8.1. Controller Interface 5.8.2. AUX Interface 5.8.3. Video Interface 5.8.4. TX Transceiver Interface 5.8.5. Transceiver Reconfiguration Interface 5.8.6. Transceiver Analog Reconfiguration Interface 5.8.7. Secondary Stream Interface 5.8.8. Audio Interface
5.8.3. Video Interface x
5.8.3.1. Video Interface (TX Video IM Enable = 0) 5.8.3.2. Video Interface (TX Video IM Enable = 1)
6. DisplayPort Sink x
6.1. Transceiver to IP Parallel Data Interface Width 6.2. Sink Embedded DisplayPort (eDP) Support 6.3. Sink Non-GPU Mode Support 6.4. HDCP 1.3 RX Architecture 6.5. HDCP 2.3 RX Architecture 6.6. Sink Interfaces 6.7. Sink Clock Tree
6.6. Sink Interfaces x
6.6.1. Controller Interface 6.6.2. AUX Interface 6.6.3. Debugging Interface 6.6.4. Video Interface 6.6.5. Clocked Video Input Interface 6.6.6. RX Transceiver Interface 6.6.7. Transceiver Reconfiguration Interface 6.6.8. Secondary Stream Interface 6.6.9. Audio Interface 6.6.10. Non-GPU Mode EDID Interface 6.6.11. MSA Interface
6.6.2. AUX Interface x
6.6.2.1. AUX Debug Interface 6.6.2.2. EDID Interface
6.6.3. Debugging Interface x
6.6.3.1. Link Parameters Interface 6.6.3.2. Video Stream Out Interface
7. DisplayPort Intel® FPGA IP Parameters x
7.1. DisplayPort Intel® FPGA IP Source Parameters 7.2. DisplayPort Intel® FPGA IP Sink Parameters
8. DisplayPort Intel® FPGA IP Simulation Example x
8.1. Design Walkthrough
8.1. Design Walkthrough x
8.1.1. Copy the Simulation Files to Your Working Directory 8.1.2. Generate the IP Simulation Files and Scripts, and Compile and Simulate 8.1.3. View the Results
9. DisplayPort API Reference x
9.1. Using the Library 9.2. btc_dprx_syslib API Reference 9.3. btc_dprx_aux_get_request 9.4. btc_dprx_aux_handler 9.5. btc_dprx_aux_post_reply 9.6. btc_dprx_baseaddr 9.7. btc_dprx_dpcd_gpu_access 9.8. btc_dprx_edid_set 9.9. btc_dprx_hpd_get 9.10. btc_dprx_hpd_pulse 9.11. btc_dprx_hpd_set 9.12. btc_dprx_lt_eyeq_init 9.13. btc_dprx_lt_force 9.14. btc_dprx_rtl_ver 9.15. btc_dprx_sw_ver 9.16. btc_dprx_syslib_add_rx 9.17. btc_dprx_syslib_info 9.18. btc_dprx_syslib_init 9.19. btc_dprx_syslib_monitor 9.20. btc_dprx_mst_link_addr_rep_set 9.21. btc_dprx_mst_conn_stat_notify_req 9.22. btc_dprx_mst_conn_stat_notify_rep 9.23. btc_dptx_syslib API Reference 9.24. btc_dptx_aux_i2c_read 9.25. btc_dptx_aux_i2c_write 9.26. btc_dptx_aux_read 9.27. btc_dptx_aux_write 9.28. btc_dptx_baseaddr 9.29. btc_dptx_edid_block_read 9.30. btc_dptx_edid_read 9.31. btc_dptx_fast_link_training 9.32. btc_dptx_hpd_change 9.33. btc_dptx_is_link_up 9.34. btc_dptx_link_bw 9.35. btc_dptx_link_training 9.36. btc_dptx_rtl_ver 9.37. btc_dptx_set_color_space 9.38. btc_dptx_sw_ver 9.39. btc_dptx_syslib_add_tx 9.40. btc_dptx_syslib_init 9.41. btc_dptx_syslib_monitor 9.42. btc_dptx_test_autom 9.43. btc_dptx_video_enable 9.44. btc_dptx_mst_allocate_payload_rep 9.45. btc_dptx_mst_allocate_payload_req 9.46. btc_dptx_mst_clear_payload_table_rep 9.47. btc_dptx_mst_clear_payload_table_req 9.48. btc_dptx_mst_conn_stat_notify_req 9.49. btc_dptx_mst_down_rep_irq 9.50. btc_dptx_mst_enable 9.51. btc_dptx_mst_enum_path_rep 9.52. btc_dptx_mst_enum_path_req 9.53. btc_dptx_mst_get_msg_transact_ver_rep 9.54. btc_dptx_mst_get_msg_transact_ver_req 9.55. btc_dptx_mst_link_address_rep 9.56. btc_dptx_mst_link_address_req 9.57. btc_dptx_mst_remote_dpcd_wr_rep 9.58. btc_dptx_mst_remote_dpcd_wr_req 9.59. btc_dptx_mst_remote_i2c_rd_rep 9.60. btc_dptx_mst_remote_i2c_rd_req 9.61. btc_dptx_mst_set_color_space 9.62. btc_dptx_mst_tavgts_set 9.63. btc_dptx_mst_up_req_irq 9.64. btc_dptx_mst_vcpid_set 9.65. btc_dptx_mst_vcptab_addvc 9.66. btc_dptx_mst_vcptab_clear 9.67. btc_dptx_mst_vcptab_delvc 9.68. btc_dptx_mst_vcptab_update 9.69. btc_dptxll_syslib API Reference 9.70. btc_dptxll_hpd_change 9.71. btc_dptxll_hpd_irq 9.72. btc_dptxll_mst_cmp_ports 9.73. btc_dptxll_mst_edid_read_rep 9.74. btc_dptxll_mst_edid_read_req 9.75. btc_dptxll_mst_get_device_ports 9.76. btc_dptxll_mst_set_csn_callback 9.77. btc_dptxll_mst_topology_discover 9.78. btc_dptxll_stream_allocate_rep 9.79. btc_dptxll_stream_allocate_req 9.80. btc_dptxll_stream_calc_VCP_size 9.81. btc_dptxll_stream_delete_rep 9.82. btc_dptxll_stream_delete_req 9.83. btc_dptxll_stream_get 9.84. btc_dptxll_stream_set_color_space 9.85. btc_dptxll_stream_set_pixel_rate 9.86. btc_dptxll_sw_ver 9.87. btc_dptxll_syslib_add_tx 9.88. btc_dptxll_syslib_init 9.89. btc_dptxll_syslib_monitor 9.90. btc_dpxx_syslib Additional Types 9.91. btc_dprx_syslib Supported DPCD Locations
10. DisplayPort Source Register Map and DPCD Locations x
10.1. Source General Registers 10.2. Source MSA Registers 10.3. Source Link PHY Control and Status 10.4. Source Timestamp 10.5. Source CRC Registers 10.6. Source Audio Registers 10.7. Source MST Registers 10.8. Source AUX Controller Interface 10.9. Source-Supported DPCD Locations
10.1. Source General Registers x
10.1.1. DPTX_TX_CONTROL 10.1.2. DPTX_TX_STATUS 10.1.3. DPTX_TX_VERSION
10.2. Source MSA Registers x
10.2.1. DPTX0_MSA_MVID 10.2.2. DPTX0_MSA_NVID 10.2.3. DPTX0_MSA_HTOTAL 10.2.4. DPTX0_MSA_VTOTAL 10.2.5. DPTX0_MSA_HSP 10.2.6. DPTX0_MSA_HSW 10.2.7. DPTX0_MSA_HSTART 10.2.8. DPTX0_MSA_VSTART 10.2.9. DPTX0_MSA_VSP 10.2.10. DPTX0_MSA_VSW 10.2.11. DPTX0_MSA_HWIDTH 10.2.12. DPTX0_MSA_VHEIGHT 10.2.13. DPTX0_MSA_MISC0 10.2.14. DPTX0_MSA_MISC1 10.2.15. DPTX0_MSA_COLOR 10.2.16. DPTX0_VBID
10.3. Source Link PHY Control and Status x
10.3.1. DPTX_PRE_VOLT0/DPTX_REG_TXFFE0 10.3.2. DPTX_PRE_VOLT1/DPTX_REG_TXFFE1 10.3.3. DPTX_PRE_VOLT2/DPTX_REG_TXFFE2 10.3.4. DPTX_PRE_VOLT3/DPTX_REG_TXFFE3 10.3.5. DPTX_RECONFIG 10.3.6. DPTX_TEST_80BIT_PATTERN1/DPTX_TEST_264BIT_PATTERN1 10.3.7. DPTX_TEST_80BIT_PATTERN2/DPTX_TEST_264BIT_PATTERN2 10.3.8. DPTX_TEST_80BIT_PATTERN3/DPTX_TEST_264BIT_PATTERN3 10.3.9. DPTX_TEST_264BIT_PATTERN4 10.3.10. DPTX_TEST_264BIT_PATTERN5 10.3.11. DPTX_TEST_264BIT_PATTERN6 10.3.12. DPTX_TEST_264BIT_PATTERN7 10.3.13. DPTX_TEST_264BIT_PATTERN8 10.3.14. DPTX_TEST_264BIT_PATTERN9
10.7. Source MST Registers x
10.7.1. DPTX_MST_VCPTAB0 10.7.2. DPTX_MST_VCPTAB1 10.7.3. DPTX_MST_VCPTAB2 10.7.4. DPTX_MST_VCPTAB3 10.7.5. DPTX_MST_VCPTAB4 10.7.6. DPTX_MST_VCPTAB5 10.7.7. DPTX_MST_VCPTAB6 10.7.8. DPTX_MST_VCPTAB7 10.7.9. DPTX_MST_TAVG_TS
10.8. Source AUX Controller Interface x
10.8.1. DPTX_AUX_CONTROL 10.8.2. DPTX_AUX_COMMAND 10.8.3. DPTX_AUX_BYTE0 10.8.4. DPTX_AUX_BYTE1 10.8.5. DPTX_AUX_BYTE2 10.8.6. DPTX_AUX_BYTE3 10.8.7. DPTX_AUX_BYTE4 10.8.8. DPTX_AUX_BYTE5 10.8.9. DPTX_AUX_BYTE6 10.8.10. DPTX_AUX_BYTE7 10.8.11. DPTX_AUX_BYTE8 10.8.12. DPTX_AUX_BYTE9 10.8.13. DPTX_AUX_BYTE10 10.8.14. DPTX_AUX_BYTE11 10.8.15. DPTX_AUX_BYTE12 10.8.16. DPTX_AUX_BYTE13 10.8.17. DPTX_AUX_BYTE14 10.8.18. DPTX_AUX_BYTE15 10.8.19. DPTX_AUX_BYTE16 10.8.20. DPTX_AUX_BYTE17 10.8.21. DPTX_AUX_BYTE18 10.8.22. DPTX_AUX_RESET
11. DisplayPort Sink Register Map and DPCD Locations x
11.1. Sink General Registers 11.2. Sink Timestamp 11.3. Sink Bit-Error Counters 11.4. FEC Registers 11.5. 128B/132B Link Quality Test Pattern Registers 11.6. Sink MSA Registers 11.7. Sink Audio Registers 11.8. Sink MST Registers 11.9. Sink AUX Controller Interface 11.10. Sink CRC Registers 11.11. Sink-Supported DPCD Locations
11.1. Sink General Registers x
11.1.1. DPRX_RX_CONTROL 11.1.2. DPRX_RX_STATUS 11.1.3. DPRX_BER_CONTROL 11.1.4. DPRX_BER_CNT0 11.1.5. DPRX_BER_CNT1
11.3. Sink Bit-Error Counters x
11.3.1. DPRX_BER_CNTI0 11.3.2. DPRX_BER_CNTI1
11.4. FEC Registers x
11.4.1. DPRX_FEC_CONFIG 11.4.2. DPRX_FEC_ERROR_COUNT
11.5. 128B/132B Link Quality Test Pattern Registers x
11.5.1. DPRX_BER_TEST_PATTERN
11.6. Sink MSA Registers x
11.6.1. DPRX0_MSA_MVID 11.6.2. DPRX0_MSA_NVID 11.6.3. DPRX0_MSA_HTOTAL 11.6.4. DPRX0_MSA_VTOTAL 11.6.5. DPRX0_MSA_HSP 11.6.6. DPRX0_MSA_HSW 11.6.7. DPRX0_MSA_HSTART 11.6.8. DPRX0_MSA_VSTART 11.6.9. DPRX0_MSA_VSP 11.6.10. DPRX0_MSA_VSW 11.6.11. DPRX0_MSA_HWIDTH 11.6.12. DPRX0_MSA_VHEIGHT 11.6.13. DPRX0_MSA_MISC0 11.6.14. DPRX0_MSA_MISC1 11.6.15. DPRX0_MSA_COLOR 11.6.16. DPRX0_VBID
11.7. Sink Audio Registers x
11.7.1. DPRX0_AUD_MAUD 11.7.2. DPRX0_AUD_NAUD 11.7.3. DPRX0_AUD_AIF0 11.7.4. DPRX0_AUD_AIF1 11.7.5. DPRX0_AUD_AIF2 11.7.6. DPRX0_AUD_AIF3 11.7.7. DPRX0_AUD_AIF4
11.8. Sink MST Registers x
11.8.1. DPRX_MST_VCPTAB0 11.8.2. DPRX_MST_VCPTAB1 11.8.3. DPRX_MST_VCPTAB2 11.8.4. DPRX_MST_VCPTAB3 11.8.5. DPRX_MST_VCPTAB4 11.8.6. DPRX_MST_VCPTAB5 11.8.7. DPRX_MST_VCPTAB6 11.8.8. DPRX_MST_VCPTAB7
11.9. Sink AUX Controller Interface x
11.9.1. DPRX_AUX_CONTROL 11.9.2. DPRX_AUX_STATUS 11.9.3. DPRX_AUX_COMMAND 11.9.4. DPRX_AUX_BYTE0 11.9.5. DPRX_AUX_BYTE1 11.9.6. DPRX_AUX_BYTE2 11.9.7. DPRX_AUX_BYTE3 11.9.8. DPRX_AUX_BYTE4 11.9.9. DPRX_AUX_BYTE5 11.9.10. DPRX_AUX_BYTE6 11.9.11. DPRX_AUX_BYTE7 11.9.12. DPRX_AUX_BYTE8 11.9.13. DPRX_AUX_BYTE9 11.9.14. DPRX_AUX_BYTE10 11.9.15. DPRX_AUX_BYTE11 11.9.16. DPRX_AUX_BYTE12 11.9.17. DPRX_AUX_BYTE13 11.9.18. DPRX_AUX_BYTE14 11.9.19. DPRX_AUX_BYTE15 11.9.20. DPRX_AUX_BYTE16 11.9.21. DPRX_AUX_BYTE17 11.9.22. DPRX_AUX_BYTE18 11.9.23. DPRX_AUX_I2C0 11.9.24. DPRX_AUX_I2C1 11.9.25. DPRX_AUX_RESET 11.9.26. DPRX_AUX_HPD
1. DisplayPort Intel® FPGA IP Quick Reference
2. About This IP
3. Getting Started
4. DisplayPort Intel® FPGA IP Hardware Design Examples
5. DisplayPort Source
6. DisplayPort Sink
7. DisplayPort Intel® FPGA IP Parameters
8. DisplayPort Intel® FPGA IP Simulation Example
9. DisplayPort API Reference
10. DisplayPort Source Register Map and DPCD Locations
11. DisplayPort Sink Register Map and DPCD Locations
12. DisplayPort Intel® FPGA IP User Guide Archives
13. Document Revision History for the DisplayPort Intel® FPGA IP User Guide

6.4. HDCP 1.3 RX Architecture

The HDCP 1.3 receiver block decrypts the protected video and secondary data, including main stream attributes (MSA), from the connected HDCP 1.3 device. The HDCP 1.3 receiver block has identical structure layers as the HDCP 1.3 transmitter block.
Figure 32. Architecture Block Diagram of HDCP 1.3 RX IP

The HDCP 1.3 RX core is fully autonomous. For DisplayPort application, the HDCP transmitter and the HDCP receiver communicates the HDCP register values over the AUX channel. Turn on the Enable GPU control parameter and use a Nios® II processor to drive the HDCP 1.3 RX core through the HDCP Register Port ( Avalon® memory-mapped interface). The HDCP Register Port is not exposed and will be automatically driven when you enable the Support HDCP 1.3 parameter.

The HDCP specifications requires the HDCP 1.3 RX core to be programmed with the DCP-issued production key – Device Private Keys (Bkeys) and Key Selection Vector (Bksv). The IP retrieves the key from the on-chip memory externally to the core through the HDCP Key Port (rx_hdcp interface). The on-chip memory must store the key data in the arrangement shown in the table below.

Table 36.  HDCP 1.3 RX Key Port Addressing
Address Content
6'h28 {16’d0, Bksv[39:0]}
6'h27 Bkeys39[55:0]
6'h26 Bkeys38[55:0]
... ...
6'h01 Bkeys01[55:0]
6'h00 Bkeys00[55:0]

The Video Stream and Secondary Data Layer receives audio and video content over its Video and Secondary Data Input Port, and performs the decryption operation. The Video Stream and Secondary Data Layer detects the Encryption Status Signaling (ESS) provided by the DisplayPort IP to determine when to decrypt frames.

To implement the HDCP 1.3 RX core as a repeater upstream interface, the IP must propagate certain information such as KSV list and Bstatus to the upstream transmitter and to be used for SHA-1 hash digest. The repeater downstream interface (TX) must provide this information through the Repeater Message Port (rx_rpt_msg interface) using the Avalon® memory-mapped interface. You can use the same clock source to drive the clocking for the HDCP Register Port (or the controller interface of the DisplayPort Intel® FPGA IP) and Repeater Message Port.

The mapping for the RX registers defined in the following table is equivalent to the address space for HDCP 1.3 receiver defined in the HDCP specification.

Table 37.  HDCP 1.3 RX Register Mapping
Address Register R/W Reset Bit Bit Name Description
0x00 BKSV0 RO – 7:0 – Bit [7:0] of HDCP Receiver KSV.
0x01 BKSV1 7:0 Bit [15:8] of HDCP Receiver KSV.
0x02 BKSV2 7:0 Bit [23:16] of HDCP Receiver KSV.
0x03 BKSV3 7:0 Bit [31:24] of HDCP Receiver KSV.
0x04 BKSV4 7:0 Bit [39:32] of HDCP Receiver KSV.
0x05 RO_PRIME0 RO 0x00 7:0 – Authentication response. Bit [7:0] of RO’.
0x06 RO_PRIME1 7:0 – Authentication response. Bit [15:8] of RO’.
0x07 AKSV0 WO 0x00 7:0 – Bit [7:0] of HDCP Transmitter KSV.
0x08 AKSV1 7:0 Bit [15:8] of HDCP Transmitter KSV.
0x09 AKSV2 7:0 Bit [23:16] of HDCP Transmitter KSV.
0x0A AKSV3 7:0 Bit [31:24] of HDCP Transmitter KSV.
0x0B AKSV4 7:0 Bit [39:32] of HDCP Transmitter KSV.
0x0C AN0 WO 0x00 7:0 – Bit [7:0] of HDCP Session Random Number An.
0x0D AN1 7:0 Bit [15:8] of HDCP Session Random Number An.
0x0E AN2 7:0 Bit [23:16] of HDCP Session Random Number An.
0x0F AN3 7:0 Bit [31:24] of HDCP Session Random Number An.
0x10 AN4 7:0 Bit [39:32] of HDCP Session Random Number An.
0x11 AN5 7:0 Bit [47:40] of HDCP Session Random Number An.
0x12 AN6 7:0 Bit [55:48] of HDCP Session Random Number An.
0x13 AN7 7:0 Bit [63:56] of HDCP Session Random Number An.
0x14 V_PRIME_H0_0 RO 0x00 7:0 – H0 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H0 value.
0x15 V_PRIME_H0_1 7:0 Bit [15:8] of H0 value.
0x16 V_PRIME_H0_2 7:0 Bit [23:16] of H0 value.
0x17 V_PRIME_H0_3 7:0 Bit [31:24] of H0 value.
0x18 V_PRIME_H1_0 RO 0x00 7:0 – H1 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H1 value.
0x19 V_PRIME_H1_1 7:0 Bit [15:8] of H1 value.
0x1A V_PRIME_H1_2 7:0 Bit [23:16] of H1 value.
0x1B V_PRIME_H1_3 7:0 Bit [31:24] of H1 value.
0x1C V_PRIME_H2_0 RO 0x00 7:0 – H2 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H2 value.
0x1D V_PRIME_H2_1 7:0 Bit [15:8] of H2 value.
0x1E V_PRIME_H2_2 7:0 Bit [23:16] of H2 value.
0x1F V_PRIME_H2_3 7:0 Bit [31:24] of H2 value.
0x20 V_PRIME_H3_0 RO 0x00 7:0 – H3 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H3 value.
0x21 V_PRIME_H3_1 7:0 Bit [15:8] of H3 value.
0x22 V_PRIME_H3_2 7:0 Bit [23:16] of H3 value.
0x23 V_PRIME_H3_3 7:0 Bit [31:24] of H3 value.
0x24 V_PRIME_H4_0 RO 0x00 7:0 – H4 part of SHA-1 hash value used in the authentication protocol HDCP repeaters. Bit [7:0] of H4 value.
0x25 V_PRIME_H4_1 7:0 Bit [15:8] of H4 value.
0x26 V_PRIME_H4_2 7:0 Bit [23:16] of H4 value.
0x27 V_PRIME_H4_3 7:0 Bit [31:24] of H4 value.
0x28 BCAPS RO 0x000 7:2 Reserved

These bits read as 0.
1 REPEATER

HDCP repeater capability.

0 = Receiver is not a repeater.

1 = Receiver is a repeater.
0 HDCP_CAPABLE This bit reads as 1.
0x29 BSTATUS RO 0x00 7:4 Reserved These bits read as 0.
3 REAUTHENTICATION_REQUEST Refer to HDCP on DisplayPort specification version 1.3 for more information.
2 LINK_INTEGRITY_FAILURE
1 RO'_AVAILABLE
0 READY
0x2A BINFO0 RO 0x00 7 MAX_DEVS_EXCEEDED Topology error indicator. When set to 1, more than 127 downstream devices are attached.
6:0 DEVICE_COUNT Total number of attached downstream devices. Always zero for HDCP receivers. This count does not include the HDCP repeater itself, but only the downstream devices from the HDCP repeater.
0x2B BINFO1 RO 0x00 7:4 Reserved These bits read as 0.
3 MAX_CASCADE_EXCEEDED Topology error indicator. When set to 1, more than 7 levels of video repeater are cascaded together.
2:0 DEPTH 3-bit repeater cascade depth. This value gives the number of attached levels throughout the connection topology.
0x2C KSV_FIFO RO 0x00 7:0 – Key selection vector FIFO. Used to pull downstream KSVs from HDCP repeaters using auto-incrementing address. All bytes read as 0x00 for HDCP receivers that are not HDCP repeaters (REPEATER=0).
0x3E CTRL WO 0x00 31 Reserved Reserved.
30 CP_IRQ_DET Set to 1 to reset the CP_IRQ_STATUS flag in the STATUS register.
29 KSV_FIFO_OFFSET_RST Set to 1 to reset the offset of the KSV_FIFO register.
28 EXIT_AUTH Exit authenticated state.
27:0 Reserved Reserved.
0x3F STATUS RO 0x00 31:20 Reserved Reserved.
19 AUTHENTICATED

0: HDCP 1.3x event is in authenticated state.

1: HDCP 1.3x event is in unauthenticated state.
18 CP_IRQ_STATUS

0: No HDCP 1.3 event.

1: An HDCP 1.3 event occurred and HPD interrupts were generated.

17:0 Reserved Reserved.
Table 38.  HDCP 1.3 RX Repeater Register Mapping
Address Register R/W Reset Bit Bit Name Description
0x00 RPT_KSV_LIST WO 0x00000000 31:8 Reserved Reserved
7:0 KSV_LIST Byte write KSV List in big endian order.
0x01 RPT_BSTATUS RW 0x00000000 31:19 Reserved Reserved
18 REQUEST Read-only. Asserted by the core to request for KSV_LIST and BSTATUS. This usually happens when re-authentication is triggered by the connected upstream. Note that when REQUEST is asserted, the READY should also be asserted.
17 READY Read-only. Asserted by the core to indicate KSV_LIST and BSTATUS are processed. Write KSV_LIST and BSTATUS after this bit is asserted.
16 VALID Set to 1 after KSV_LIST and BSTATUS are written. Self-cleared by the core after KSV_LIST and BSTATUS are read.
15:0 BSTATUS

[15:12]: Reserved.

[11]: MAX_CASCADE_EXCEEDED

[10:8]: DEPTH

[7]: MAX_DEVS_EXCEEDED

[6:0]: DEVICE_COUNT

0x02 RPT_MISC RW – 31:1 Reserved Reserved.
0 REPEATER

Set to 0 if no downstream is connected or if the connected downstream is not HDCP 1.3-capable. This means the receiver IP is an end-point receiver rather than a repeater.

Set to 1 if the connected downstream is HDCP-capable.

Level Two Title