DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022

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Document Table of Contents

5.8.4. TX Transceiver Interface

The transceiver or Native PHY IP core instance is no longer instantiated within the DisplayPort Intel® FPGA IP.

The DisplayPort Intel® FPGA IP uses a soft 8B/10B encoder for DP1.4. This interface provides TX encoded video data (tx_parallel_data) in either dual symbol (20-bit) or quad symbol (40-bit) mode in DP1.4 and drives the digital reset (tx_digitalreset), analog reset (tx_analogreset), and PLL powerdown signals (tx_pll_powerdown) of the transceiver.

When 128B/132B channel coding is used, the 32-bit symbol (per lane) is muxed to the 40-bit wide interface (tx_parallel_data) to the transceiver. The transceiver then needs to be dynamically reconfigured between 32-bit PMA width (128B/132B channel coding) and 40-bit PMA width (8B/10B channel coding). The Enable Simplified Data Interface must be disabled to expose a static width (tx_parallel_data) port.