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- 4.1. DisplayPort Intel® FPGA IP Hardware Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-Tile Devices
6.6.8. Secondary Stream Interface
The secondary streams data can be received through the rxN_ss interfaces. The interfaces do not allow for back-pressure and assume the downstream logic can handle complete packets. The rxN_ss interface does not distinguish between the types of packets it receives.
The format of the rxN_ss interface output corresponds to four 15-nibble code words as specified by the VESA DisplayPort Standard version 1.2a, Section 220.127.116.11. These 15-nibble code words are typically supplied to the downstream Reed-Solomon decoder. The format differs for both header and payload, as shown in the following figure.
The following figure shows a typical secondary stream packet with the four byte header (HB0, HB1, HB2, and HB3) and 32-byte payload (DB0, ..., DB31). Each symbol has an associated parity nibble (PB0, ..., PB11). Downstream logic uses start-of-packet and end-of-packet to determine if the current input is a header or payload symbol.
Data is clocked out of the rxN_ss port using the rx_ss_clk signal. This signal is the same phase and frequency as the main link lane 0 clock.
The PB* fields of the Secondary Stream interface contain different information depending on the specific channel coding. 8B/10B SDPs carry the Parity Byte while 128B/132B typically carries zeros (0). When SDP CRC16 is enabled for 128B/132B Channel Coding, the fields for PB8, PB9, PB10, and PB11 contains the CRC16 values instead of zeros (0).
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