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- 4.1. DisplayPort Intel® FPGA IP Hardware Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-Tile Devices
6.6.9. Audio Interface
The audio interfaces are downstream from the secondary stream decoder. They extract and decode the Audio InfoFrame packets, Audio Timestamp packets, and Audio Sample data.
The Audio Timestamp packet payload contains M and N values, which the sink uses to recover the source’s audio sample clock. The rxN_audio port uses the values to generate the rxN_audio_valid signal according to sample audio data. Data is clocked out using the rx_ss_clk signal. The rx_ss_clk signal comes from the rx parallel clock from the RX transceiver. This clock runs at link data rate/20 for dual symbol mode and link data rate/40 for quad symbol mode.
The sink generates the rxN_audio_valid signal using the M and N values, and asserts it at the current audio sample clock rate. The rxN_audio_mute signal indicates whether audio data is present on the DisplayPort interface.
The captured Audio InfoFrame is available on the audio port. The 5-byte port corresponds to the 5 bytes used in the Audio InfoFrame (refer to CEA-861-D). The Audio InfoFrame describes the type of audio content.
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