DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Give Feedback

11.7.1. DPRX0_AUD_MAUD

Received audio Maud register, DPRX0_AUD_MAUD.

Address: 0×0030

Direction: RO

Reset: 0×00000000

Table 159.  DPRX0_AUD_MAUD Bits

Bit

Bit Name

Function

31:24

Unused

23:0

MAUD/AFREQ[23:0]

8B/10B Channel Coding:

Received audio Maud

128B/132B Channel Coding:

Received audio AFREQ[23:0]