DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022
Public

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6.6.6. RX Transceiver Interface

The transceiver or Native PHY IP core instance is no longer instantiated within the DisplayPort Intel® FPGA IP. The DisplayPort Intel® FPGA IP uses a soft 8B/10B decoder for DP1.4. This interface receives RX transceiver recovered data (rx_parallel_data) in either dual symbol (20-bit) or quad symbol (40-bit) mode in DP1.4. The DisplayPort Intel® FPGA IP drives the digital reset (rx_digitalreset), analog reset (rx_analogreset), and controls the CDR circuitry locking mode.

When 128B/132B channel coding is used, the 32-bit symbols (per lane) is muxed to the 40-bit wide interface (rx_parallel_data) from the transceiver. The transceiver then needs to be dynamically reconfigured between 32-bit PMA width (128B/132B channel coding) and 40-bit PMA width (8B/10B channel coding). The Enable Simplified Data Interface must be disabled to expose a static width (rx_parallel_data) port.