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- 4.1. DisplayPort Intel® FPGA IP Hardware Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-Tile Devices
5.2. Main Data Path
The main link data path consists of the video packetizer, video geometry measurement, audio and secondary stream encoder, and training and link quality patterns generator.
The IP multiplexes data from these four paths and transmits it through a scrambler and a data encoder depending on the DP channel coding, DP2.0 is 128B/132B and DP1.4 is 8B/10B encoding.
At DP1.4 link rates, all the symbols transmitted during video display period and video blanking period are skewed by two Link symbol period between adjacent lanes.
DP2.0 link rates does not require inter-lane skewing; thus, all symbols appear at the same cycle across all lanes. However, DP2.0 uses a different scrambler seed on all lanes, thus the scrambler symbols will have different values across all lanes even though they have the same value prior to scrambling.
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