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- 4.1. DisplayPort Intel® FPGA IP Hardware Design Examples for Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10, and Intel® Agilex™ F-Tile Devices
18.104.22.168. DP2.0 (128B/132B Channel Coding)
The IP composes Link Layer Frames - consisting of a LLCP (Link Layer Control Packet), followed by 1024 MTPs (Multi-stream Transport Packets). Each DP2.0 MTP is 64 link symbol clocks in length, time-multiplexed to carry the data (video, MSA, secondary, blanking) streams. Additional symbols called PHY_SYNC symbols and Overhead Symbols are then inserted into the Link Layer Frames before being sent to the 128B/132B Logical PHY Layer for encoding.
- Logical lane count (always 4) to physical lane count (1, 2, or 4) conversion
- Intra Super Symbol Shifting: moving control symbols to the first of every super symbol
- PHY_SYNC Generator: replaces PHY_SYNCs from the Link Layer with the appropriate one to be transmitted on the wire
- CDI bit insertion: 4-bit during Link Training, 1-bit during regular operation
- FEC Encoding
This produces a 32-bit symbol sent to the Intel FPGA high-speed transceiver.
During Link Training, the Logical PHY Layer generates both the 128b/132b_TPS1 and 128b/132b_TPS2 symbols.
- 128b/132b_TPS1 link training pattern (Nyquist pattern)
- 12bb/132b_TPS2 link training pattern
- PRBS7, PRBS9, PRBS11, PRBS15, PRBS23, PRBS31 pattern
- Custom 264-bit repeating pattern
- Square wave pattern
All patterns are as defined in the DP2.0 Specification UHBRx Link Quality Test Support.
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