DisplayPort Intel® FPGA IP User Guide

ID 683273
Date 1/24/2022
Public

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10.2.15. DPTX0_MSA_COLOR

Address: 0x002e

Direction: RW

Reset: 0x00000001

Table 77.  DPTX0_MSA_COLOR Bits

Bit

Bit Name

Function

31:14

Unused

13

USE_VSC_SDP

0 = use MISC0

1 = use VSC SDP

Note: If you configure this bit to use VSC SDP, refer to the VESA DisplayPort Standard version 1.4 for the VSC SDP Payload Pixel Encoding/Colorimetry Format. Y-Only and Raw format are not supported.

12

DYNAMIC_RANGE

  • 0 = VESA (from 0 to maximum)
  • 1 = CEA range

11:8

COLORIMETRY

  • 0000 = ITU-R BT601-5
  • 0001 = ITU-R BT709-5
Note: Refer to Table 2–120 bit[3:0] in the VESA DisplayPort Standard version 1.4 for all colorimetry support including BT.2020.
7:4

ENCODING

  • 0000 = RGB
  • 0001 = YCbCr 4:4:4
  • 0010 = YCbCr 4:2:2
  • 0011 = YCbCr 4:2:0
3

Unused

 
2:0

BPC

Bits per pixel format

  • 000 = 6 bpc
  • 001 = 8 bpc
  • 010 = 10 bpc
  • 011 = 12 bpc
  • 100 = 16 bpc