Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 4/13/2024
Document Table of Contents

7.2.1. Clock Domains

Figure 49. Clock Domains and Clock Generation for the Application LayerThe following illustrates the clock domains when using coreclkout_hip to drive the Application Layer and the pld_clk of the IP core. The Intel-provided example design connects coreclkout_hip to the pld_clk. However, this connection is not mandatory. Inside the Hard IP for PCI Express* , the blocks shown in white are in the pclk domain, while the blocks shown in yellow are in the coreclkout_hip domain.

As this figure indicates, the IP core includes the following clock domains: pclk, coreclkout_hip and pld_clk.