Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 11/29/2023
Public
Document Table of Contents

5.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals

The optional CRA port for the full-featured IP core allows upstream PCI Express devices and external Avalon-MM masters to access internal control and status registers. Both Endpoint and Root Port applications can use the CRA interface.

Table 25.  Avalon-MM CRA Slave Interface Signals

Signal Name

Direction

Description

cra_irq_O

Output

Interrupt request. A port request for an Avalon-MM interrupt.

cra_readdata_o[31:0]

Output

Read data lines.

cra_waitrequest_o

Output

Wait request to hold off more requests.

cra_address_i[13:0]

Input

An address space of 16,384 bytes is allocated for the control registers. Avalon-MM slave addresses provide address resolution down to the width of the slave data bus. Because all addresses are byte addresses, this address logically goes down to bit 2. Bits 1 and 0 are 0. To read or write individual bytes of a dword, use byte enables. For example, to write bytes 0 and 1, set cra_byteenable_i[3:0]= 4'b0011 . Refer to Valid Byte Enable Configurations for valid byte enable patterns.

cra_byteenable_i[3:0]

Input

Byte enable.

cra_chipselect_i

Input

Chip select signal to this slave.

cra_read_i

Input

Read enable.

cra_write_i

Input

Write request.

cra_writedata_i[31:0]

Input

Write data.

The CRA write request uses the high to low transition of CraWaitRequest_o to signal transaction completion

Figure 28. CRA Write Transaction

The CRA read transaction has similar timings to the CRA write transaction. The CraReadData_o[31:0] signals are valid at the clock cycle when CraWaitRequest_o is low. You can use the first rising clock edge after CraWaitRequest_o goes low to latch the data.

Figure 29. CRA Read Transaction