Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 4/13/2024
Document Table of Contents

3.3. Base Address Register (BAR) Settings

You can configure up to six 32-bit BARs or three 64-bit BARs.

Table 13.  BAR Registers






64-bit prefetchable memory

32-bit non-prefetchable memory

32-bit prefetchable memory

I/O address space

Defining memory as prefetchable allows data in the region to be fetched ahead anticipating that the requestor may require more data from the same region than was originally requested. If you specify that a memory is prefetchable, it must have the following 2 attributes:
  • Reads do not have side effects
  • Write merging is allowed

The 32-bit prefetchable memory and I/O address space BARs are only available for the Legacy Endpoint.


Not configurable

Specifies the memory size calculated from other parameters you enter.