14. Avalon-MM Testbench and Design Example for Root Port
Starting with the 18.0 release of Intel® Quartus® Prime, the Root Port design example is available for the following variants of the Intel® Arria® 10 Avalon® -MM Hard IP for PCIe:
To generate an Avalon® -MM Root Port design example, configure the IP Core as a Root Port and select the Avalon® -MM application interface type. For more details, refer to the following Example Design Generation section.
The simulation testbench instantiates a Root Port design example of the Avalon® -MM Intel® Arria® 10 Hard IP for PCIe and an Endpoint BFM, which sets up all the basic configuration registers in the Root Port. This configuration allows the Root Port to initiate link training and bus enumeration.
You can compile the Root Port design example to generate the .sof file, which you can program into your FPGA device to perform board-level hardware tests. For simulation, the Root Port design example uses a JTAG master bridge BFM to configure the Root Port and initiate link training and bus enumeration. The JTAG master bridge BFM can also drive the TXS Avalon® -MM interface to perform memory reads and writes.
The testbench and Root Port design example provide a simple method to do basic testing of the application layer logic that interfaces with the IP Core. The Endpoint BFM allows you to create and run simple task stimuli with configurable parameters to exercise the basic functionality of the design example. The testbench and BFM are not intended to be a substitute for a full verification environment, and do not cover corner cases and certain traffic profiles. To ensure the best verification coverage possible, Intel recommends that you obtain commercially available PCI Express* verification IP and tools to run simulations, or do your own extensive hardware testing, or both.
Overview of the Design Example
Overview of the Simulation Testbench
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