A.5.4. Interrupt Handler Block
The interrupt handler implements both INTX and MSI interrupts. The msi_enable bit in the configuration register specifies the interrupt type. The msi_enable_bit is part of the MSI message control portion in the MSI Capability structure. It is bit of address 0x050 in the Configuration Space registers. If the msi_en able bit is on, an MSI request is sent to the Intel® Arria® 10 or Intel® Cyclone® 10 GX Hard IP for PCI Express when received, otherwise INTX is signaled. The interrupt handler block supports a single interrupt source, so that software may assume the source. You can disable interrupts by leaving the interrupt signal unconnected in the IRQ column of Platform Designer.
- Sending a legacy interrupt instead of an MSI interrupt
- Sending an MSI interrupt instead of a legacy interrupt
- Loss of an interrupt request
According to the PCI Express Base Specification, if MSI_enable=0 and the Disable Legacy Interrupt bit=1 in the Configuration Space Command register (0x004), the Hard IP should not send legacy interrupt messages when an interrupt is generated.
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