Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 4/13/2024
Document Table of Contents

A.5.4. Interrupt Handler Block

The interrupt handler implements both INTX and MSI interrupts. The msi_enable bit in the configuration register specifies the interrupt type. The msi_enable_bit is part of the MSI message control portion in the MSI Capability structure. It is bit[16] of address 0x050 in the Configuration Space registers. If the msi_en able bit is on, an MSI request is sent to the Arria® 10 or Cyclone® 10 GX Hard IP for PCI Express when received, otherwise INTX is signaled. The interrupt handler block supports a single interrupt source, so that software may assume the source. You can disable interrupts by leaving the interrupt signal unconnected in the IRQ column of Platform Designer.

When the MSI registers in the Configuration Space of the Completer Only Single Dword Arria® 10 or Cyclone® 10 GX Hard IP for PCI Express are updated, there is a delay before this information is propagated to the Bridge module shown in the following figure.
Figure 79.  Platform Designer Design Including Completer Only Single Dword Endpoint for PCI Express
You must allow time for the Bridge module to update the MSI register information. Normally, setting up MSI registers occurs during enumeration process. Under normal operation, initialization of the MSI registers should occur substantially before any interrupt is generated. However, failure to wait until the update completes may result in any of the following behaviors:
  • Sending a legacy interrupt instead of an MSI interrupt
  • Sending an MSI interrupt instead of a legacy interrupt
  • Loss of an interrupt request

According to the PCI Express Base Specification, if MSI_enable=0 and the Disable Legacy Interrupt bit=1 in the Configuration Space Command register (0x004), the Hard IP should not send legacy interrupt messages when an interrupt is generated.