Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 4/13/2024
Document Table of Contents

9.1. Physical Layer Errors

Table 70.  Errors Detected by the Physical Layer The following table describes errors detected by the Physical Layer. Physical Layer error reporting is optional in the PCI Express Base Specification.




Receive port error


This error has the following 3 potential causes:

  • Physical coding sublayer error when a lane is in L0 state. These errors are reported to the Hard IP block via the per lane PIPE interface input receive status signals, rxstatus<lane_number>[2:0] using the following encodings:
    • 3'b100: 8B/10B Decode Error
    • 3'b101: Elastic Buffer Overflow
    • 3'b110: Elastic Buffer Underflow
    • 3'b111: Disparity Error
  • Deskew error caused by overflow of the multilane deskew FIFO.
  • Control symbol received in wrong lane.