Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 4/13/2024
Document Table of Contents

5.5. Reset, Status, and Link Training Signals

Refer to Reset and Clocks for more information about the reset sequence and a block diagram of the reset logic.

Table 29.  Reset Signals






Active low reset signal. In the Intel hardware example designs, npor is the OR of pin_perst and local_rstn coming from the software Application Layer. If you do not drive a soft reset signal from the Application Layer, this signal must be derived from pin_perst. You cannot disable this signal. Resets the entire IP Core and transceiver. Asynchronous.

This signal is edge, not level sensitive; consequently, you cannot use a low value on this signal to hold custom logic in reset. For more information about the reset controller, refer to Reset.



Active low reset signal. It is derived from npor or pin_perstn. You can use this signal to reset the Application Layer.


Active low reset from the PCIe reset pin of the device. pin_perst resets the datapath and control registers. Configuration via Protocol (CvP) requires this signal. For more information about CvP refer to Arria 10 CvP Initialization and Partial Reconfiguration via Protocol User Guide.

Arria® 10 devices can have up to 4 instances of the Hard IP for PCI Express IP core. Each instance has its own pin_perst signal. Cyclone® 10 GX have a single instance of the Hard IP for PCI Express IP core. You must connect the pin_perst of each Hard IP instance to the corresponding nPERST pin of the device. These pins have the following locations:

  • NPERSTL0: bottom left Hard IP and CvP blocks
  • NPERSTL1: top left Hard IP block
  • NPERSTR0: bottom right Hard IP block
  • NPERSTR1: top right Hard IP block

For example, if you are using the Hard IP instance in the bottom left corner of the device, you must connect pin_perst to NPERSL0.

For maximum use of the Arria® 10 or Cyclone® 10 GX device, Intel recommends that you use the bottom left Hard IP first. This is the only location that supports CvP over a PCIe link. If your design does not require CvP, you may select other Hard IP blocks.

Refer to the Arria 10 GX, GT, and SX Device Family Pin Connection Guidelines or Cyclone® 10 GX Device Family Pin Connection Guidelines for more detailed information about these pins.

Figure 31. Reset and Link Training Timing Relationships

The following figure illustrates the timing relationship between npor and the LTSSM L0 state.

Note: To meet the 100 ms system configuration time, you must use the fast passive parallel configuration scheme with CvP and a 32-bit data width (FPP x32) or use the Arria® 10 or Cyclone® 10 GX Hard IP for PCI Express in autonomous mode.