Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 4/13/2024
Document Table of Contents

3.2. Avalon-MM Settings

Table 12.  Avalon-MM Settings
Parameter Value Description
Avalon-MM address width



Specifies the address width for Avalon-MM RX master ports that access Avalon-MM slaves in the Avalon address domain.

When you select Enable Avalon-MM DMA or Enable non-bursting Avalon-MM slave interface with individual byte access (TXS), this value must be set to 64.

Enable completer-only Endpoint On/Off In completer-only mode, the Hard IP can receive requests, but cannot initiate upstream requests. However, it can transmit completion packets on the PCI Express TX link. This mode removes the Avalon-MM TX slave port and thereby reduces logic utilization.
Enable completer-only Endpoint with 4-byte payload On/Off

This is a non-pipelined version of Completer Only mode. At any time, only a single request can be outstanding. Single DWORD completer uses fewer resources than Completer Only. This variant is targeted for systems that require simple read and write register accesses from a host CPU. If you select this option, the width of the data for RXM BAR masters is always 32 bits, regardless of the Avalon-MM width.

For the Avalon-MM interface with DMA, this value must be Off.

Enable control register access (CRA) Avalon-MM slave port On/Off

Allows read and write access to bridge registers from the interconnect fabric using a specialized slave port. This option is required for Requester/Completer variants and optional for Completer Only variants. Enabling this option allows read and write access to bridge registers, except in the Completer‑Only single DWORD variations.

Export MSI/MSI-X conduit interfaces On/Off

When you turn this option On, the core exports top‑level MSI and MSI‑X interfaces that you can use to implement a Custom Interrupt Handler for MSI and MSI‑X interrupts. For more information about the Custom Interrupt Handler, refer to Interrupts for End Points Using the Avalon-MM Interface with Multiple MSI/MSI‑X Support. If you turn this option Off, the core handles interrupts internally.

Enable PCIe interrupt at power-on On/Off

When you turn this option On, the Avalon‑MM Arria® 10 or Cyclone® 10 GX Hard IP for PCI Express the interrupt register is enabled at power-up. Turning off this option disables the interrupt register at power‑up. The setting does not affect run‑time configuration of the interrupt enable register.

For the Avalon-MM interface with DMA, this value must be Off.

Enable hard IP status bus when using the Avalon-MM interface On/Off When you turn this option On, your top-level variant includes signals that are useful for debugging, including link training and status, and error signals. The following signals are included in the top-level variant:
  • Link status signals
  • ECC error signals
  • LTSSM signals
  • Configuration parity error signal
Address width of accessible PCIe memory space 20-64 Specifies the number of bits necessary to access the PCIe address space.