Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 4/13/2024
Document Table of Contents

2.3. Generating the Design

  1. Launch Platform Designer.
    • If you have an existing .qsys file in your directory, the Open System dialog box appears. Click New to specify a Quartus Prime project name and custom IP variation name for your design. Then, click Create.
    • If not, a new project is automatically created. Save it before moving to the next step.
  2. In the IP Catalog, locate and select Arria® 10/Cyclone 10 Hard IP for PCI Express. The parameter editor appears.
  3. On the IP Settings tabs, specify the parameters for your IP variation.
  4. In the Connections panel, make the following dummy connection: rxm_bar0 to txs slave interface.
    Platform Designer determines the size of the Avalon® -MM BAR master from its connection to an Avalon® -MM slave device. When you generate the example design, this connection is removed.
  5. Remove the clock_in and reset_in components that were instantiated by default.
  6. On the Example Design tab, the PIO design is available for your IP variation.
  7. For Example Design Files, select the Simulation and Synthesis options.
  8. For Generated HDL Format, only Verilog is available.
  9. For Target Development Kit, select the Arria® 10 GX FPGA Development Kit option. Currently, there is no option to select an Cyclone® 10 GX Development Kit when generating an example design.
  10. Click Generate Example Design. The software generates all files necessary to run simulations and hardware tests on the Arria® 10 FPGA Development Kit.