Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 11/29/2023
Public
Document Table of Contents
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B.1. TLP Packet Formats without Data Payload

The following figures show the header format for TLPs without a data payload.

Figure 80. Memory Read Request, 32-Bit Addressing
Figure 81. Memory Read Request, Locked 32-Bit Addressing
Figure 82. Memory Read Request, 64-Bit Addressing
Figure 83. Memory Read Request, Locked 64-Bit Addressing
Figure 84. Configuration Read Request Root Port (Type 1)
Figure 85. I/O Read Request
Figure 86. Message without Data

Figure 87. Completion without Data
Figure 88. Completion Locked without Data