Arria® 10 and Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 4/13/2024
Document Table of Contents

A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing

Note: The PCI Express-to-Avalon-MM bridge supports both 32- and 64-bit addresses. If you select 64-bit addressing the bridge does not perform address translation.

When you specify 32-bit addresses, the Avalon-MM address of a received request on the TX Avalon‑MM slave port is translated to the PCI Express address before the request packet is sent to the Transaction Layer. You can specify up to 512 address pages and sizes ranging from 4 KB to 4 GB when you customize your Avalon‑MM Arria® 10 or Cyclone® 10 GX Hard IP for PCI Express as described in Avalon to PCIe Address Translation Settings . This address translation process proceeds by replacing the MSB of the Avalon‑MM address with the value from a specific translation table entry; the LSB remains unchanged. The number of MSBs to be replaced is calculated based on the total address space of the upstream PCI Express devices that the Avalon‑MM Hard IP for PCI Express can access. The number of MSB bits is defined by the difference between the maximum number of bits required to represent the address space supported by the upstream PCI Express device minus the number of bits required to represent the Size of address pages which are the LSB pass-through bits (N). The Size of address pages (N) is applied to all entries in the translation table.

Each of the 512 possible entries corresponds to the base address of a PCI Express memory segment of a specific size. The segment size of each entry must be identical. The total size of all the memory segments is used to determine the number of address MSB to be replaced. In addition, each entry has a 2-bit field, Sp[1:0], that specifies 32-bit or 64-bit PCI Express addressing for the translated address. The most significant bits of the Avalon-MM address are used by the interconnect fabric to select the slave port and are not available to the slave. The next most significant bits of the Avalon-MM address index the address translation entry to be used for the translation process of MSB replacement.

For example, if the core is configured with an address translation table with the following attributes:

  • Number of Address Pages16
  • Size of Address Pages1 MB
  • PCI Express Address Size64 bits

then the values in the following figure are:

  • N = 20 (due to the 1 MB page size)
  • Q = 16 (number of pages)
  • M = 24 (20 + 4 bit page selection)
  • P = 64

In this case, the Avalon address is interpreted as follows:

  • Bits [31:24] select the TX slave module port from among other slaves connected to the same master by the system interconnect fabric. The decode is based on the base addresses assigned in Platform Designer.
  • Bits [23:20] select the address translation table entry.
  • Bits [63:20] of the address translation table entry become PCI Express address bits [63:20].
  • Bits [19:0] are passed through and become PCI Express address bits [19:0].

The address translation table is dynamically configured at run time. The address translation table is implemented in memory and can be accessed through the CRA slave module. Dynamic configuration is optimal in a typical PCI Express system where address allocation occurs after BIOS initialization.

Figure 77. Avalon-MM-to-PCI Express Address Translation
The following figure depicts the Avalon-MM-to-PCI Express address translation process. In this figure the variables represent the following parameters:
  • N—the number of pass-through bits.
  • M—the number of Avalon-MM address bits.
  • P—the number of PCIe address bits.
  • Q—the number of translation table entries.
  • Sp[1:0]—the space indication for each entry.