Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 11/29/2023
Public
Document Table of Contents
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14.1.1. Example Design Generation

To generate an Intel® Arria® 10 Root Port design example, do the following steps:
  1. Open Platform Designer.
  2. In the Platform Designer IP Catalog, select Intel Arria 10/Cyclone 10 Hard IP for PCI Express.
  3. After the altera_pcie_a10_hip IP GUI opens, select the following parameters in the System Settings tab under IP Settings:
    1. For Application interface type, select Avalon® -MM.
    2. For Hard IP mode, select any variant.
    3. For Port type, select Root port.
  4. In the Base Address Registers tab, only enable BAR0, or BAR0 and BAR1. All other BARs are disabled in the current Root Port design example.
    1. If you set BAR0 to use 64-bit prefetchable memory, you need to disable BAR1.
    2. If you set BAR0 to use 32-bit prefetchable memory or 32-bit non-prefetchable memory, you can enable or disable BAR1.
    3. The BAR0 and BAR1 sizes are not configurable in the current Intel® Arria® 10 PCIe IP GUI. After you generate the design example, you can open it using Platform Designer and reselect the memory size. The BAR size is then automatically updated.
  5. Click the Generate Example Design button. A small window appears allowing you to select the directory to generate the Root Port design example, and give a name to the design example.
  6. Click OK in the Select Example Design Directory window to let Platform Designer generate a design example for you.