Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 6/03/2021
Document Table of Contents

A.5.3. TX Block

The TX block sends completion information to the Avalon‑MM Hard IP for PCI Express which sends this information to the root complex. The TX completion block generates a completion packet with Completer Abort (CA) status and no completion data for unsupported requests. The TX completion block also supports the zero‑length read (flush) command.

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