Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 6/03/2021
Document Table of Contents

A.5.5. Preliminary Support for Root Port

This release adds preliminary support for a Gen3 x4, Gen3 x8, and Gen2 x8 Root Port with a 256-bit Avalon-MM interface to the Application Layer.

This Avalon-MM Root Port Supports the following features:

  • RX Master Module (HPRXM) —This 256-bit bursting Avalon-MM master port propagates PCI Express requests, converting them to bursting read or write requests to the interconnect fabric.
  • TX Slave Module (TXS) —This optional non-bursting 32-bit Avalon-MM slave port propagates single dword read and write requests from the interconnect fabric to the PCI Express link. The bridge translates requests from the interconnect fabric to PCI Express request packets.
  • Control Register Access Slave Module—This optional, 32-bit Avalon-MM slave port provides access to internal control and status registers from external Avalon-MM masters. The CRA port supports single dword TLPS, including MemRd, MemWr, Message, and Configuration requests. It does not support bursting.
  • Read/Write Data Movers
  • Byte enable is supported on the 256-bit interface only.
    • On the Receive (RX) side:
      • For memory read requests, byte enable is supported for up to 8 DWs that results in a burst count of 1 on the Avalon-MM interface.
        • If the address is 256-bit aligned (i.e. ending in 'h00, 'h20, 'h40 and so on), the maximum read request size (MRRS) with byte enable is 8 DWs.
        • Unaligned addresses will limit the MRRS. For example, an address ending in 'h04 limits the MRRS to 7 DWs to have the byte enable take effect. Similarly, an address ending in 'h08 limits the MRRS to 6 DWs, while one ending in 'h0C limits the MRRS to 5 DWs, and so on.
      • For memory write requests, there are no limits, meaning that byte enable is supported up to the requester's maximum payload size (MPS).
    • On the Transmit (TX) side, whether or not byte enable is supported depends on your implementation choice.

This preliminary release Gen3 Avalon-MM Root Port has the following limitations:

  • It does not support legacy interrupts.
  • RX flush requests (i.e. requests with fbe = 0, lbe = 0, and length = 1) are not supported.
  • The TX Slave (TXS) Module does not support bursting on either the 256-bit interface or the 128-bit interface.
  • The TX Slave Module supports native PCI Express addresses. It does not translate Avalon-MM addresses to the PCI Express address space.

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