Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-Mapped (Avalon-MM) Interface for PCI Express* User Guide

ID 683724
Date 6/03/2021
Document Table of Contents

7.2.2. Clock Summary

Table 68.  Clock Summary



Clock Domain


62.5, 125 or 250 MHz

Avalon‑ST interface between the Transaction and Application Layers.


pld_clk has a maximum frequency of 250 MHz and a minimum frequency that can be equal or more than the coreclkout_hip frequency, depending on the link width, link rate, and Avalon® interface width as indicated in the table for the Application Layer clock frequency above.

Application and Transaction Layers.


100 MHz

SERDES (transceiver). Dedicated free running input clock to the SERDES block.

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